AT90USB162-16MU Atmel, AT90USB162-16MU Datasheet
AT90USB162-16MU
Specifications of AT90USB162-16MU
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AT90USB162-16MU Summary of contents
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... Operating temperature – Industrial (-40°C to +85°C) • Maximum Frequency – 8 MHz at 2.7V - Industrial range – 16 MHz at 4.5V - Industrial range ® 8-Bit Microcontroller 8-bit Microcontroller with 8/16K Bytes of ISP Flash and USB Controller AT90USB82 AT90USB162 Preliminary 7707A–AVR–03/07 ...
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Pin Figure 1. Pinout AT90USB82/162 Configurations XTAL1 1 (PC0) XTAL2 2 GND 3 VCC 4 QFN32 (PCINT11) PC2 5 (OC.0B / INT0) PD0 6 (AIN0 / INT1) PD1 7 (RXD1 / AIN1 / ...
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Overview The AT90USB82/162 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By exe- cuting powerful instructions in a single clock cycle, the AT90USB82/162 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to ...
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... Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel AT90USB82/162 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AT90USB82/162 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emula- tors, and evaluation kits ...
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Pin Descriptions VCC Digital supply voltage. GND Ground. Port B (PB7..PB0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink ...
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About Code This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files Examples and interrupt handling in C ...
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AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and ...
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Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of these address pointers can also be used as an address pointer for look up ...
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Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter- rupt enable control is then performed in separate control registers. If the Global Interrupt Enable ...
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General Purpose Working Registers Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 4, each register is also assigned a data memory ...
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The X-register, Y- The registers R26..R31 have some added functions to their general purpose usage. These reg- register, and Z-register isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and ...
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Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Har- vard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain MIPS per MHz with the corresponding unique ...
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The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that ...
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TABLE 2. Assembly Code Example sei sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example __enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ ...
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AVR This section describes the different memories in the AT90USB82/162. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the AT90USB82/162 AT90USB82/162 features an EEPROM Memory for data storage. All three ...
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SRAM Data Figure 9 shows how the AT90USB82/162 SRAM Memory is organized. Memory The AT90USB82/162 is a complex microcontroller with more peripheral units than can be sup- ported within the 64 location reserved in the Opcode for the IN and ...
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Figure 9. Data Memory Map 7707A–AVR–01/07 D ata M emory $0000 - $001F 32 R egisters $0020 - $005F 64 I/O R egisters 160 $0060 - $00FF $0100 I nternal S RAM (512 x ...
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Data Memory Access This section describes the general access timing concepts for internal memory access. The Times internal data SRAM access is performed in two clk Figure 10. On-chip Data SRAM Access Cycles EEPROM Data The AT90USB82/162 contains 512 bytes ...
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The EEPROM Address Bit Register – EEARH and EEARL Read/Write Initial Value • Bits 15..12 – Res: Reserved Bits These bits are reserved bits in the AT90USB82/162 and will always read as zero. • Bits 11..0 – EEAR8..0: EEPROM Address ...
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Table 1. EEPROM Mode Bits EEPM1 • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero ...
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The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The ...
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The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glo- bally) so that no interrupts will occur during execution of these functions. ...
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The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...
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All AT90USB82/162 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the ...
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System Clock and Clock Options Clock Systems Figure 11 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks ...
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Clock Switch In the AT90USB82/162 product, the Clock Multiplexer and the System Clock Prescaler can be modified by software. Exemple of use The modification can occur when the device enters in USB Suspend mode. It then switches from External Clock ...
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Clock switch Algorythm Swith from external if (Usb_suspend_detected()) clock to RC clock { } Switch from RC clock to if (Usb_wake_up_detected()) external clock { } Clock Selection Bit Register 0 – CLKSEL0 Read/Write Initial Value • Bit 7-6 – RCSUT[1:0]: ...
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The OSCE bit must be written to logic one to enable External Oscillator / Low Power Oscillator. The OSCE bit must be written to logic zero to disable the External Oscillator / Low Power Oscillator. • Bit 0 – CLKS: ...
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Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 3. Device ...
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The recommended oscillator start-up time is dependent on the clock type, and varies from 6 cycles for an externally applied clock to 32K cycles for a low frequency crystal. The start-up sequence for the clock includes both ...
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Table 6. Start-up Times for the Low Power Crystal Oscillator Clock Selection Oscillator Source / Power Conditions Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Ceramic resonator, BOD enabled Ceramic resonator, fast rising power Ceramic resonator, slowly rising ...
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Reset Time-out. For more information on the pre-programmed calibration value, see the sec- tion “Calibration Byte” on page 236 Table 8. Internal Calibrated RC Oscillator Operating Modes Notes: When this Oscillator is selected, start-up times are determined by the ...
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External Clock The device can utilize a external clock source as shown in Figure 15. To run the device on an external clock, the CKSEL Fuses must be programmed as shown in Table 3. Figure 15. External Clock Drive Configuration ...
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When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock ...
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Table 11. Clock Prescaler Select CLKPS3 7707A–AVR–01/07 CLKPS2 CLKPS1 CLKPS0 ...
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PLL The PLL is used to generate internal high frequency (48 MHz) clock for USB interface, the PLL input is generated from an external low-frequency (the crystal oscillator or external clock input pin from XTAL1). Internal PLL for USB The ...
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Table 12. PLL input prescaler configurations (Continued) PLLP2 • Bit 1 – PLLE: PLL Enable When the PLLE is set, the PLL is started and if needed internal RC Oscillator is started as a PLL reference clock. ...
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Power The AT90USB82/162 product includes an internal 5V to 3.3V regulator that Distribution allows to supply the USB pad (see Figure 17.) and, depending on the applica- tion, external components or even the microcontroller itself (see Figure 18.). USB or ...
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UVCC UCAP PS/2 Pad 3.3V Reg USB Pad UVSS Figure 19. 3.3V configuration Important note: In the 3.3V configuration, the internal regulator is bypassed. The regulator has to be disabled to avoid extra power consumption. Regulator Control Bit Register – ...
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Power Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- Management tion to the application’s requirements. and Sleep To ...
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Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing the USB, SPI, USART, Analog Comparator, Timer/Counters, Watchdog, and the interrupt system to continue operating. This ...
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Power-save mode with the exception that the Oscillator is kept running. From Extended Standby mode, the device wakes up in six clock cycles. Table 14. Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Sleep Mode Idle Power-down ...
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Power Reduction The Power Reduction Register, PRR, provides a method to stop the clock to individual peripher- Register als to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or ...
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Power Reduction Bit Register 1 - PRR1 Read/Write Initial Value • Bit 7 - PRUSB: Power Reduction USB Writing a logic one to this bit shuts down the USB by stopping the clock to the module. When waking up the ...
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Enable and Sleep Modes” on page 68 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to V input buffer will use ...
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System Control and Reset Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute ...
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Figure 20. Reset Logic BODLEVEL [2..0] Table 15. Reset Characteristics Symbol V POT V RST t RST Notes: Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table 15. ...
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Figure 21. MCU Start-up, RESET Tied to V TIME-OUT INTERNAL Figure 22. MCU Start-up, RESET Extended Externally TIME-OUT INTERNAL External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum ...
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Brown-out Detection. The hysteresis on the detection level should be interpreted BOT Table 16. BODLEVEL Fuse Coding BODLEVEL 2..0 Fuses Note: Table 17. Brown-out Characteristics Symbol V HYST t BOD When the BOD is enabled, ...
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Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t on page 52 for details ...
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This bit is reserved. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • Bit ...
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Watchdog Timer AT90USB82/162 has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms to ...
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In the same operation, write a logic one to the Watchdog change enable bits WDCE and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit and even if it will ...
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The following code example shows one assembly and one C function for turning off the Watch- dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of ...
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The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. TABLE 2. Assembly Code Example WDT_Prescaler_Change: C Code Example void WDT_Prescaler_Change(void Note: Note: The Watchdog Timer should be ...
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Watchdog Timer Bit Control Register - WDTCSR Read/Write Initial Value • Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs twice in the Watchdog Timer and if the Watchdog Timer is configured for interrupt. ...
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Watchdog Timer Clock Bit Divider Register - WDTCKD Read/Write Initial Value • Bit 7-4 - Reserved bits These bits are reserved and will always read as zero. • Bit 3 - WDEWIF: Watchdog Early Warning Interrupt Flag This bit is ...
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Table 20. Watchdog Timer Prescale Select, DIV = 0 (CLKwdt = CLK128 / 1) WDP3 WDP2 WDP1 WDP0 ...
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WDP3 WDP2 WDP1 WDP0 Table 22. Watchdog Timer Prescale Select, DIV = 2 (CLKwdt = CLK128 ...
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Table 23. Watchdog Timer Prescale Select, DIV = 3 (CLKwdt = CLK128 / 7) WDP3 WDP2 WDP1 WDP0 ...
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Interrupts This section describes the specifics of the interrupt handling as performed in AT90USB82/162. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12. Interrupt Vectors in AT90USB82/162 Table 24. Reset and ...
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Notes: Table 25 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at ...
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Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is ...
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Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI ...
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Ports as General The ports are bi-directional I/O ports with optional internal pull-ups. Figure 29 shows a functional Digital I/O description of one I/O-port pin, here generically called Pxn. Figure 29. General Digital I/O Note: Configuring the Pin Each port ...
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Switching Between When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} Input and Output = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) occurs. Normally, ...
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Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the ...
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TABLE 3. Assembly Code Example ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi ldi out out ; Insert nop for synchronization nop ; Read port pins in ... C Code Example unsigned char ...
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The simplest method to ensure a defined level of an unused pin enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important recommended to ...
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Table 27 summarizes the function of the overriding signals. The pin and port indexes from Fig- ure 32 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 27. ...
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MCU Control Register Bit – MCUCR Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured ...
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MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a slave, ...
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Table 30 relate the alternate functions of Port B to the overriding signals shown in Figure 32 on page 69. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI ...
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Table 31. Port C Pins Alternate Functions The alternate pin configuration is as follows: • ICP1/INT4/CLK0, Bit 7 ICP1, Input Capture pin 1 :The PC7 pin can act as an input capture for Timer/Counter1. INT4, External Interrupt source 4 : ...
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Table 32 and Table 33 relate the alternate functions of Port C to the overriding signals shown in Figure 32 on page 69. Table 32. Overriding Signals for Alternate Functions in PC7..PC4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV ...
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Alternate Functions of The Port D pins with alternate functions are shown in Table 34. Port D Table 34. Port D Pins Alternate Functions Port Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 The alternate pin configuration is as ...
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AIN1, Analog Comparator Negative input. This pin is directly connected to the negative input of the Analog Comparator. RXD1, USART1 Receive Data : When the USART1 Receiver is enabled, this pin is configured as an input regardless of DDRD2. When ...
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Table 36. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: 78 PD2/INT2/RXD1/A PD3/INT3/TXD1 IN1 TXEN1 RXEN1 0 PORTD2 • PUD TXEN1 RXEN1 1 0 TXEN1 0 TXD1 0 ...
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Register Description for I/O-Ports Port B Data Register – Bit PORTB Read/Write Initial Value Port B Data Direction Bit Register – DDRB Read/Write Initial Value Port B Input Pins Bit Address – PINB Read/Write Initial Value Port C Data Register ...
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Port D Input Pins Bit Address – PIND Read/Write Initial Value PIND7 PIND6 PIND5 PIND4 PIND3 R/W R/W R/W R/W R/W N/A N/A N/A N/A N PIND2 PIND1 PIND0 PIND R/W ...
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External The External Interrupts are triggered by the INT7:0 pin or any of the PCINT12..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 or PCINT12..0 pins are configured as Interrupts outputs. This feature provides a ...
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Note: Table 38. Asynchronous External Interrupt Characteristics Symbol t INT External Interrupt Bit Control Register B – EICRB Read/Write Initial Value • Bits 7..0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt Sense Control Bits The External ...
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External Interrupt Flag Bit Register – EIFR Read/Write Initial Value • Bits 7..0 – INTF7 - INTF0: External Interrupt Flags When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0 becomes set ...
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Read/Write Initial Value • Bit 4..0 – PCINT12..8: Pin Change Enable Mask 12..8 Each PCINT12..8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT12..8 is set and the PCIE1 bit in PCICR is set, ...
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Timer/Counter0 Timer/Counter0 and 1 share the same prescaler module, but the Timer/Counters can have dif- ferent prescaler settings. The description below applies to all Timer/Counters used as a and general name Timer/Counter1 Prescalers ...
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However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances recommended that maximum frequency of an external clock source is less than f ...
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Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event man- Timer/Counter0 agement) and wave generation. The main features are: with PWM • Two ...
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Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com- pare Unit, in this case Compare ...
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Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02 the timer is stopped. However, ...
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The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is disabled. The double buffering synchronizes the update ...
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Figure 38. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or out- put) ...
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Normal Mode The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit ...
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OCR0A is set to zero (0x00). The waveform frequency is defined by the following clk_I/O equation: The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the ...
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OC0B pin (See Table 42 on page 98). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by ...
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Figure 41. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches ...
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The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. Timer/Counter The Timer/Counter is a ...
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Figure 45 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where OCR0A is TOP. Figure 45. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- caler (f clk_I/O clk ...
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Timer/Counter Register Description Timer/Counter Control Bit Register A – TCCR0A Read/Write Initial Value • Bits 7:6 – COM01A:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 ...
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Table 43 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Table 43. Compare Output Mode, Phase Correct PWM Mode COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match ...
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Table 43 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Table 46. Compare Output Mode, Phase Correct PWM Mode COM0A1 Note: • Bits 3, 2 – Res: Reserved ...
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Timer/Counter Control Bit Register B – TCCR0B Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, ...
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Table 48. Clock Select Bit Description (Continued) CS02 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature ...
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Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt ...
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The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: Timer/Counter • True 16-bit Design (i.e., Allows 16-bit PWM) (Timer/Counter1 • Three independent Output Compare Units • Double ...
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Figure 46. 16-bit Timer/Counter Block Diagram Note: Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Reg- ister (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are described ...
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The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input Capture pin (ICPn the Analog Comparator pins (See “Analog Comparator” on page 215.) The Input Capture unit ...
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Assembly Code Examples C Code Examples Note: The assembly code example returns the TCNTn value in the r17:r16 register pair important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the two instructions ...
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The following code examples show how atomic read of the TCNTn Register contents. Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNTn: ; Save global interrupt ...
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The following code examples show how atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNTn: C Code Example void ...
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Timer/Counter The Timer/Counter can be clocked by an internal or an external clock source. The clock source Clock Sources is selected by the Clock Select logic which is controlled by the Clock Select (CSn2:0) bits located in the Timer/Counter control ...
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The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. Input Capture Unit The Timer/Counter incorporates an input capture unit that can capture ...
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The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for defining the counter’s TOP value. In these cases the Waveform Genera- tion mode (WGMn3:0) bits must be set before the TOP ...
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Flag generates an Output Compare interrupt. The OCFnx Flag is automatically cleared when the interrupt is executed. Alternatively the OCFnx Flag can be cleared by software by writ- ing a logical one to its I/O bit location. The Waveform ...
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The high byte (OCRnxH) has to be written first. When the high byte I/O location is written by the CPU, the TEMP Register will be updated by the value ...
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Compare Match The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses Output Unit the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx pin ...
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A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOCnx strobe bits. Modes of ...
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Figure 51. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn Flag according to the register used to define ...
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OCRnA set to MAX). The PWM resolution in bits can be calculated by using the following equation: In fast PWM mode the counter is incremented until the counter value matches either one of the ...
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Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively ...
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TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 53. The figure shows phase correct PWM mode ...
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The actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at the compare ...
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Figure 54. Phase and Frequency Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM). ...
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The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal ...
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Figure 57. Timer/Counter Timing Diagram, no Prescaling (CTC and FPWM) (PC and PFC PWM) and ICFn Figure 58 shows the same timing data, but with the prescaler enabled. 124 clk I/O clk Tn (clk /1) I/O TCNTn TOP - 1 ...
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Figure 58. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOVn and ICF n as TOP) OCRnx (Update at TOP) 7707A–AVR–01/07 I/O Tn /8) I/O TOP - 1 TOP - ...
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Timer/Counter Register Description Timer/Counter1 Control Register A – Bit TCCR1A Read/Write Initial Value • Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A • Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B • Bit 3:2 – ...
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Table 50. Compare Output Mode, non-PWM COMnA1/COMnB1/ COMnC1 Table 51 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM mode. Table 51. Compare Output Mode, Fast PWM COMnA1/COMnB1/ COMnC0 Note: Table 52 shows ...
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Table 52. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM COMnA1/COMnB/ COMnC1 Note: • Bit 1:0 – WGMn1:0: Waveform Generation Mode Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting sequence ...
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Table 53. Waveform Generation Mode Bit Description WGMn2 WGMn1 Mode WGMn3 (CTCn) (PWMn1 ...
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When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the input cap- ture function is disabled. • Bit 5 – Reserved ...
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Bit 4:0 – Reserved Bits These bits are reserved for future use. For ensuring compatibility with future devices, these bits must be written to zero when TCCRnC is written. Timer/Counter1 – Bit TCNT1H and TCNT1L Read/Write Initial Value The ...
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Output Compare Bit Register 1 A – OCR1AH and OCR1AL Read/Write Initial Value Output Compare Bit Register 1 B – OCR1BH and OCR1BL Read/Write Initial Value Output Compare Bit Register 1 C – OCR1CH and OCR1CL Read/Write Initial Value The ...
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Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The ...
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This flag is set in the timer clock cycle after the counter (TCNTn value matches the Output Com- pare Register A (OCRnA). Note that a Forced Output Compare (FOCnA) strobe will not set the OCFnA Flag. OCFnA is automatically cleared ...
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Serial The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the A T90 twe e n ...
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Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line. This ...
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The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and ...
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TABLE 2. Assembly Code Example SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi out ; Enable SPI, Master, set clock rate fck/16 ldi out ret SPI_MasterTransmit: ; Start transmission of data (r16) out Wait_Transmit: ; Wait for ...
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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. TABLE 2. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 7707A–AVR–01/07 ...
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SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the ...
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SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas- ter mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. ...
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SPI Status Register – Bit SPSR Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global ...
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Table 59. CPOL Functionality CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 Figure 61. SPI Transfer Format with CPHA = 0 Figure 62. SPI Transfer Format with CPHA = 1 7707A–AVR–01/07 Leading Edge Sample (Rising) Setup (Rising) Sample (Falling) Setup ...
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USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or ...
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Figure 63. USART Block Diagram Note: The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock Generation ...
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Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USARTn supports four modes of clock operation: Normal asynchronous, Double Speed asyn- chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART ...
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Internal Clock Internal clock generation is used for the asynchronous and the synchronous master modes of Generation – The operation. The description in this section refers to Figure 64. Baud Rate Generator The USART Baud Rate Register (UBRRn) and the ...
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Double Speed The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has Operation (U2Xn) effect for the asynchronous operation. Set this bit to zero when using synchronous operation. Setting this bit will ...
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A frame starts with the start bit followed by the least significant data bit. Then the next data bits total of nine, are succeeding, ...
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Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the initialization. Before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. ...
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XCKn pin will be overridden and used as transmission clock. Sending Frames with A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The 5 to ...
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For the assembly code, the data to be sent is assumed to be stored in registers R17:R16. TABLE 4. Assembly Code Example USART_Transmit: ; Wait for empty transmit buffer sbis UCSRnA,UDREn rjmp USART_Transmit ...
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Transmitter Flags and The USART Transmitter has two flags that indicate its state: USART Data Register Empty Interrupts (UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts. The Data Register Empty (UDREn) Flag indicates whether the ...
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UDRn will be masked to zero. The USART has to be initialized before the function can be used. TABLE 3. Assembly Code Example USART_Receive: ; Wait for data to be received sbis UCSRnA, ...
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TABLE 2. Assembly Code Example USART_Receive: USART_ReceiveNoError: C Code Example unsigned int USART_Receive( void ) { } Note: The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an ...
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Receive Compete Flag The USART Receiver has one flag that indicates the Receiver state. and Interrupt The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist ...
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RxDn port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost Flushing the Receive The receiver buffer FIFO will be ...
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If two or more of these three samples have logical high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts looking for ...
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Receiver does not have a similar (see Table 2) base frequency, the Receiver will not be able to synchronize the frames to the start bit. The following equations can ...
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Table 2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0) # (Data+Parity Bit) Table 3. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2Xn = 1) # (Data+Parity Bit) The recommendations of the ...
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The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address frame to find out which MCU has been addressed particular slave MCU has been addressed, ...
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Figure 70. Reception Flow Control Waveform Example Figure 71. RTS behavior RTS will rise at 2/3 of the last received stop bit if the receive fifo is full. To ensure reliable transmissions, even after a RTS rise, an extra-data can ...
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For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the Receiver. The transmit buffer can only be written when the UDREn Flag in the UCSRnA Register is set. ...
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Bit 1 – U2Xn: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using syn- chronous operation. Writing this bit to one will reduce the divisor of the ...
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TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDRn. USART Control and Bit Status Register n C – ...
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The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits (Character SiZe frame the Receiver and Transmitter use. Table 7. UCSZn Bits Settings UCSZn2 • Bit 0 – UCPOLn: Clock Polarity This ...
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Read/Write Initial Value • Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRH is written. • Bit 11:0 – UBRR11:0: USART Baud Rate ...
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Table 10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% ...
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Table 11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% ...
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Table 12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% ...
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USART in SPI The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be set to a master SPI compliant mode of operation. The Master SPI Mode (MSPIM) has the follow- Mode ing features: • Full Duplex, Three-wire Synchronous ...
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SPI Data Modes There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which and Timing are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are shown in Figure 73. Data ...
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USART MSPIM The USART in MSPIM mode has to be initialized before any communication can take place. The Initialization initialization process normally consists of setting the baud rate, setting master mode of operation (by setting DDR_XCKn to one), setting frame ...
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TABLE 2. Assembly Code Example USART_Init: clr r18 out UBRRnH,r18 out UBRRnL,r18 ; Setting the XCKn port pin as output, enables master mode. sbi XCKn_DDR, XCKn ; Set MSPI mode of operation and SPI data mode 0. ldi r18, (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn) ...
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The data written to UDRn is moved from the transmit buffer to the shift register when the shift register is ready to send a new frame. Note: The following code examples show a simple USART ...
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Transmitter and The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode Receiver Flags and are identical in function to the normal USART operation. However, the receiver error status flags Interrupts (FE, DOR, and PE) are ...
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Bit 6 - TXCIEn: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt ...
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When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the data word is transmitted first. Refer to the Frame Formats section page 4 for details. • Bit 1 - ...
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USB controller Features • Support full-speed. • Support ping-pong mode (dual bank), with automatic switch • 176 bytes of DPRAM. – 1 endpoint of 64 bytes max, (default control endpoint), – 2 endpoints of 64 bytes max, (one bank), – ...
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Typical Application Implementation Depending on the USB operating mode and target application power supply, the AT90USB82/162 requires different hardware typical implementations. Figure 75. Operating modes versus frequency and power-supply 5.5 4.5 3.6 3.4 3.0 2.7 VCC min 0 Device mode ...
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Figure 77. Typical Bus powered application with 3V I/O VBUS UDM UDP UVSS Serial resistors on USB Data lines should have 22 Ohms value (+/-5%). Ucap capacitor should have 1µF (+/- 10%) value for correct operation. 7707A–AVR–01/07 VCC UCAP 1µF ...
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General Operating Modes Introduction The USB controller is disabled and reset after a hardware reset generated by: – – – – – But another available and optionnal reset source is : – In this case, the USB controller is reset, ...
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Figure 79. USB Interrupt System The macro distinguishes between USB General events in opposition with USB Endpoints events that are relevant with data transfers relatives to each endpoint. Figure 80. USB General interrupt vector sources Each of these interupts are ...
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Figure 81. USB Endpoint Interrupt vector sources OVERFI UESTAX.6 UNDERFI FLERRE UESTAX.5 UEIENX.7 NAKINI UEINTX.6 NAKINE UEIENX.6 NAKOUTI UEINTX.4 TXSTPE UEIENX.4 RXSTPI UEINTX.3 TXOUTE UEIENX.3 RXOUTI UEINTX.2 RXOUTE UEIENX.2 STALLEDI UEINTX.1 STALLEDE UEIENX.1 TXINI UEINTX.0 TXINE UEIENX.0 Each endpoint has ...
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Power modes Idle mode In this mode, the CPU core is halted (CPU clock stopped). The Idle mode is taken wether the USB controller is running or not. The CPU can wake up on any USB interrupts. Power down In ...
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When using this mode, there is no influence over the USB controller. Memory The controller does only support the following memory allocation management. management The reservation of an Endpoint can only be made in the increasing order (Endpoint 0 to ...
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Table 17. Allocation and reorganization USB memory flow Free memory EPEN=1 ALLOC=1 Endpoints activation • First, Endpoint 0 to Endpoint 4 are configured, in the growing order. The memory of each is reserved in the ...
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Figure 82. Pad behaviour The SUSPI flag indicated that a suspend state has been detected on the USB bus. This flag automatically put the USB pad in Idle. The detection of a non-idle event sets the WAKEUPI flag and wakes-up ...
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Bit Initial Val- ue • 7 – USBE: USB macro Enable Bit Set to enable the USB controller. Clear to disable and reset the USB controller, to disable the USB transceiver and to disable the USB controller clock inputs. • ...
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USB/PS2 Software Bit Output Enable register – UPOE Read/Write Initial Value • Bit 7:6 – UPOE[1:0]: USB/PS2 Output enable Set these bits with the following configuration to enable or disable the USB/PS2 software drive. UPOE1 - UPOE0 ...
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USB Software Operating modes Depending on the USB operating mode, the software should perform some the following operations: Power On the USB interface • Configure PLL interface • Enable PLL • Check PLL lock • Enable USB interface • Configure ...
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USB Device Operating modes Introduction The USB device controller supports full speed data transfers. In addition to the default control endpoint, it provides four other endpoints, which can be configured in control, bulk, interrupt or isochronous modes: • Endpoint 0: ...
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The endpoint reset may be associated with a clear of the data toggle command (RSTDT bit answer to the CLEAR_FEATURE USB command. USB reset When an USB reset is detected on the USB line (SEO state with a ...
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A clear of EPEN acts as an endpoint reset (see Section , page 192 for more details). It also per- forms the next operation: • The configuration of the endpoint is kept (EPSIZE, EPBK, ALLOC kept) • It resets the ...
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When the USB device controller is in full-speed mode, setting DETACH will disconnect the pull-up on the D+ . Then, clearing DETACH will connect the pull-up on the D+. Figure 85. Detach a device in Full-speed: Remote Wake-up The ...
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This management simplifies the enumeration process management command is not sup- ported or contains an error, the firmware set the STALL request flag and can return to the main task, waiting for the next SETUP request ...
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Control Read The next figure shows a control read transaction. The USB controller has to manage the simulta- neous write requests from the CPU and the USB host: SETUP USB line SETUP RXSTPI HW RXOUTI TXINI Wr Enable HOST Wr ...
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RXOUTI shall always be cleared before clearing FIFOCON. The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can read data from the bank, and cleared by hardware when the bank is ...
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The Endpoint must be configured first. “Manual” mode The TXINI bit is set by hardware when the current bank becomes free. This triggers an interrupt if the TXINE bit is set. The FIFOCON bit is set at the same time. ...
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If the endpoint uses 2 banks, the second one can be read by the HOST while the current is being written by the CPU. Then, when the CPU clears FIFOCON, the next bank may be already ready (free) and TXINI ...