AT90USB162-16MU Atmel, AT90USB162-16MU Datasheet - Page 185

• Manufacturer Part Number: AT90USB162-16MU
• Description: MCU AVR USB 16K FLASH 32-QFN
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB162-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, PS/2, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFN
• Controller Family/series: AVR USB
• No. Of I/o's: 22
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• Processor Series: AT90USBx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART, debugWIRE
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATSTK526, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK526 - KIT STARTER FOR AT90USB82/162ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Power modes
Idle mode
Power down
Freeze clock
Memory access
capability
7707A–AVR–01/07
In this mode, the CPU core is halted (CPU clock stopped). The Idle mode is taken wether the
USB controller is running or not. The CPU can wake up on any USB interrupts.
In this mode, the oscillator is stopped and halts all the clocks (CPU and peripherals). The USB
controller “wakes up” when:
•
The firmware has the ability to reduce the power consumption by setting the FRZCLK bit, which
freeze the clock of USB controller. When FRZCLK is set, it is still possible to access to the fol-
lowing registers:
•
•
•
•
•
Moreover, when FRZCLK is set, only the asynchronous interrupt may be triggered :
•
The CPU has the possibility to directly access to the USB internal memory (DPRAM).
The memory access mode is performed using 2 sfr’s: UDPADDH and UDPADDL.
To enter in this mode:
•
•
Even if the USBE bit is cleared, the DPACC bit and DPADD7:0 field can be used by the
firmware.
Then, a read or a write in UEDATX (device mode) is performed according to DPADD7:0 and the
base address DPADD7:0 field is automatically increased. The endpoint FIFO pointers and the
value of the UENUM registers are discarded in this mode.
The aim of this functionality is to use the DPRAM as extra-memory.
the WAKEUPI interrupt is triggered (single asynchronous interrupt)
USBCON,
DPRAM direct access registers (DPADD7:0, UEDATX)
UDCON (detach, ...)
UDINT
UDIEN
WAKEUPI
the USBE bit must be cleared.
the DPACC bit and the base address DPADD7:0 must be set.
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