AT90USB162-16MU Atmel, AT90USB162-16MU Datasheet - Page 257

• Manufacturer Part Number: AT90USB162-16MU
• Description: MCU AVR USB 16K FLASH 32-QFN
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB162-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, PS/2, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFN
• Controller Family/series: AVR USB
• No. Of I/o's: 22
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• Processor Series: AT90USBx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART, debugWIRE
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATSTK526, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK526 - KIT STARTER FOR AT90USB82/162ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

SPI Timing
Characteristics
7707A–AVR–01/07
See Figure 109 and Figure 110 for details.
Table 49. SPI Timing Parameters
Note:
Figure 109. SPI Interface Timing Requirements (Master Mode)
10
12
13
14
15
16
17
18
11
1
2
3
4
5
6
7
8
9
(Data Output)
(Data Input)
(CPOL = 0)
(CPOL = 1)
1. In SPI Programming mode the minimum SCK high/low period is:
SS high to tri-state
- 2 t
- 3 t
SCK to out high
SCK to SS high
MISO
MOSI
SCK high/low
SS low to SCK
Rise/Fall time
Rise/Fall time
SCK
SCK
SCK high/low
SS low to out
Description
SCK period
SCK period
Out to SCK
SCK to out
SCK to out
SS
CLCL
CLCL
Setup
Setup
Hold
Hold
for f
for f
CK
CK
(1)
< 12 MHz
> 12 MHz
6
4
MSB
5
MSB
Master
Master
Master
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
7
4 • t
2 • t
Min
10
t
20
20
ck
...
ck
ck
...
50% duty cycle
See Table 58
0.5 • t
TBD
TBD
Typ
10
10
10
10
15
15
10
2
sck
LSB
1
LSB
2
Max
3
8
ns
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