ATMEGA64A-AU Atmel, ATMEGA64A-AU Datasheet - Page 268

MCU AVR 64K ISP FLASH 64-TQFP

ATMEGA64A-AU

Manufacturer Part Number
ATMEGA64A-AU
Description
MCU AVR 64K ISP FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA64A-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Package
64TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
53
Interface Type
SPI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
4
Processor Series
ATMEGA64x
Core
AVR8
Data Ram Size
4 KB
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Cpu Family
ATmega
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
For Use With
770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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25.5.6
8160C–AVR–07/09
Scanning the ADC
Figure 25-9. General Boundary-scan Cell used for Signals for Comparator and ADC
Table 25-4.
Figure 25-10
The Boundary-scan cell from
not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin
as well.
Signal
Name
AC_IDLE
ACO
ACME
ACBG
shows a block diagram of the ADC with all relevant control and observe signals.
Direction as
Seen from the
Comparator
Input
Output
Input
Input
Boundary-scan Signals for the Analog Comparator
Previous
From
Cell
ShiftDR
0
1
ClockDR
Figure 25-6
Analog
Bandgap
Description
Turns off Analog
Comparator when
true
Comparator
Output
Uses output signal
from ADC mux
when true
Reference enable
D
is attached to each of these signals. The ADC need
UpdateDR
Q
Next
Cell
To
Recommended
Input when Not in
Use
1
Will become input
to µC code being
executed
0
0
D
G
Q
EXTEST
0
1
Output Values when
Recommended Inputs
are Used
Depends upon µC code
being executed
0
Depends upon µC code
being executed
Depends upon µC code
being executed
ATmega64A
268

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