ATMEGA64A-AU Atmel, ATMEGA64A-AU Datasheet - Page 337

MCU AVR 64K ISP FLASH 64-TQFP

ATMEGA64A-AU

Manufacturer Part Number
ATMEGA64A-AU
Description
MCU AVR 64K ISP FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA64A-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Package
64TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
53
Interface Type
SPI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
4
Processor Series
ATMEGA64x
Core
AVR8
Data Ram Size
4 KB
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Cpu Family
ATmega
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
For Use With
770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Table 28-7.
Notes:
28.9
Table 28-8.
Notes:
8160C–AVR–07/09
0
1
2
3a
3b
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
R
R
V
REF
AIN
INT
Symbol
1/t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
LHLL
AVLL
LLAX_ST
LLAX_LD
AVLLC
AVRL
AVWL
LLWL
LLRL
DVRH
RLDV
RHDX
RLRH
DVWL
WHDX
DVWH
WLWH
1. Minimum for AVCC is 2.7V.
2. Maximum for AVCC is 5.5V.
External Data Memory Timing
1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
CLCL
Parameter
Internal Voltage Reference
Reference Input Resistance
Analog Input Resistance
ADC Characteristics, Differential Channels, -40⋅C – 85⋅C (Continued)
External Data Memory Characteristics, 4.5 - 5.5 Volts, No Wait-state
Parameter
Oscillator Frequency
ALE Pulse Width
Address Valid A to ALE Low
Address Hold After ALE Low,
write access
Address Hold after ALE Low,
read access
Address Valid C to ALE Low
Address Valid to RD Low
Address Valid to WR Low
ALE Low to WR Low
ALE Low to RD Low
Data Setup to RD High
Read Low to Data Valid
Data Hold After RD High
RD Pulse Width
Data Setup to WR Low
Data Hold After WR High
Data Valid to WR High
WR Pulse Width
8 MHz Oscillator
57.5
57.5
47.5
47.5
42.5
Min
115
115
115
115
115
125
115
40
5
5
0
Condition
Max
67.5
67.5
75
0.5t
0.5t
0.5t
0.5t
0.5t
1.0t
1.0t
1.0t
1.0t
1.0t
1.0t
1.0t
CLCL
CLCL
CLCL
CLCL
CLCL
Min
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
0.0
40
Min
5
5
0
2.3
CLCL
Variable Oscillator
-15
-15
-20
-5
-5
-10
-10
-10
-10
-10
-10
(1)
(1)
(2)
(2)
(1)
2.56
Typ
100
32
0.5t
0.5t
ATmega64A
1.0t
CLCL
CLCL
Max
CLCL
16
Max
+5
+5
2.7
-50
(2)
(2)
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
V
337

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