ATMEGA64A-AU Atmel, ATMEGA64A-AU Datasheet - Page 270

MCU AVR 64K ISP FLASH 64-TQFP

ATMEGA64A-AU

Manufacturer Part Number
ATMEGA64A-AU
Description
MCU AVR 64K ISP FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA64A-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Package
64TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
53
Interface Type
SPI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
4
Processor Series
ATMEGA64x
Core
AVR8
Data Ram Size
4 KB
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Cpu Family
ATmega
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
For Use With
770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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8160C–AVR–07/09
Table 25-5.
Signal
Name
COMP
ACLK
ACTEN
ADCBGEN
ADCEN
AMPEN
DAC_9
DAC_8
DAC_7
DAC_6
DAC_5
DAC_4
DAC_3
DAC_2
DAC_1
DAC_0
EXTCH
G10
G20
Boundary-scan Signals for the ADC
Output
Input
Input
Input
Input
Input
Input
Input
Input
Direction
as Seen
from the
ADC
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Description
Comparator Output
Clock signal to gain
stages implemented
as Switch-cap filters
Enable path from gain
stages to the
Comparator
Enable Band-gap
reference as negative
input to Comparator
Power-on signal to the
ADC
Power-on signal to the
gain stages
Bit nine of digital value
to DAC
Bit eight of digital
value to DAC
Bit seven of digital
value to DAC
Bit six of digital value
to DAC
Bit five of digital value
to DAC
Bit four of digital value
to DAC
Bit three of digital
value to DAC
Bit two of digital value
to DAC
Bit 1 of digital value to
DAC
Bit 0 of digital value to
DAC
Connect ADC
channels 0 - 3 to
bypass path around
gain stages
Enable 10x gain
Enable 20x gain
(1)
Recommended
Input when not
in Use
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
Recommended Inputs
are Used, and CPU is
ATmega64A
Output Values when
not Using the ADC
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
270

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