ATMEGA64A-AU Atmel, ATMEGA64A-AU Datasheet - Page 310
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ATMEGA64A-AU
Manufacturer Part Number
ATMEGA64A-AU
Description
MCU AVR 64K ISP FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA64A-MUR.pdf
(21 pages)
2.ATMEGA64A-AU.pdf
(392 pages)
3.ATMEGA64A-AU.pdf
(3 pages)
Specifications of ATMEGA64A-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Package
64TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
53
Interface Type
SPI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
4
Processor Series
ATMEGA64x
Core
AVR8
Data Ram Size
4 KB
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Cpu Family
ATmega
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
For Use With
770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA64A-AU
Manufacturer:
ATMEL
Quantity:
4 500
Company:
Part Number:
ATMEGA64A-AU
Manufacturer:
Atmel
Quantity:
900
Company:
Part Number:
ATMEGA64A-AU
Manufacturer:
ATMEL85
Quantity:
900
Part Number:
ATMEGA64A-AU
Manufacturer:
AT
Quantity:
20 000
27.8
27.8.1
8160C–AVR–07/09
SPI Serial Programming Pin Mapping
SPI Serial Programming Algorithm
Even though the SPI Programming interface re-uses the SPI I/O module, there is one important
difference: The MOSI/MISO pins that are mapped to PB2 and PB3 in the SPI I/O module are not
used in the Programming interface. Instead, PE0 and PE1 are used for data in SPI Program-
ming mode as shown in
Table 27-13. Pin Mapping SPI Serial Programming
Figure 27-10. SPI Serial Programming and Verify
Note:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the ATmega64A, data is clocked on the rising edge of SCK.
When reading data from the ATmega64A, data is clocked on the falling edge of SCK. See
27-11
To program and verify the ATmega64A in the SPI Serial Programming mode, the following
sequence is recommended:
for timing details.
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
2. VCC - 0.3 < AVCC < VCC + 0.3, however, AVCC should always be within 2.7 - 5.5V.
MISO (PDO)
MOSI (PDI)
XTAL1 pin.
Symbol
SCK
Table
27-13.
MOSI
MISO
ck
ck
SCK
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
Pins
PE0
PE1
PB1
PE0
PE1
PB1
XTAL1
RESET
GND
(1)
I/O
AVCC
O
VCC
I
I
+2.7 - 5.5V
+2.7 - 5.5V
(2)
ck
ck
Serial Data Out
Serial Data In
Description
Serial Clock
ATmega64A
12 MHz
12 MHz
Figure
310