ATMEGA64A-AU Atmel, ATMEGA64A-AU Datasheet - Page 308

• Manufacturer Part Number: ATMEGA64A-AU
• Description: MCU AVR 64K ISP FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Package: 64TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 53
• Interface Type: SPI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 4
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Cpu Family: ATmega
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• For Use With: 770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8160C–AVR–07/09
Figure 27-8. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
Figure 27-9. Parallel Programming Timing, Reading Sequence (Within the Same Page) with
Note:
XTAL1
PAGEL
XTAL1
DATA
DATA
BS1
XA0
XA1
BS1
XA0
XA1
OE
1. The timing requirements shown in
1. The timing requirements shown in
ing operation.
ing operation.
Timing Requirements
ADDR0 (Low Byte)
LOAD ADDRESS
ADDR0 (Low Byte)
LOAD ADDRESS
(LOW BYTE)
(LOW BYTE)
t
XLOL
t
OLDV
(1)
(LOW BYTE)
LOAD DATA
DATA (Low Byte)
DATA (Low Byte)
(LOW BYTE)
READ DATA
Figure 27-7
Figure 27-7
t
XLXH
t
BHDV
(i.e. t
(i.e. t
(HIGH BYTE)
LOAD DATA
DATA (High Byte)
DVXH
DVXH
DATA (High Byte)
(HIGH BYTE)
READ DATA
t
XLPH
, t
, t
LOAD DATA
XHXL
XHXL
, and t
, and t
t
OHDZ
t
PLXH
ATmega64A
XLDX
XLDX
LOAD ADDRESS
LOAD ADDRESS
(LOW BYTE)
ADDR1 (Low Byte)
ADDR1 (Low Byte)
(LOW BYTE)
) also apply to read-
) also apply to load-
(1)
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