ATMEGA64A-AU Atmel, ATMEGA64A-AU Datasheet - Page 63

MCU AVR 64K ISP FLASH 64-TQFP

ATMEGA64A-AU

Manufacturer Part Number
ATMEGA64A-AU
Description
MCU AVR 64K ISP FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA64A-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Package
64TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
53
Interface Type
SPI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
4
Processor Series
ATMEGA64x
Core
AVR8
Data Ram Size
4 KB
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Cpu Family
ATmega
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
For Use With
770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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11.2.1
8160C–AVR–07/09
Moving Interrupts Between Application and Boot Space
When the BOOTRST Fuse is programmed and the Boot section size set to 8K bytes, the most
typical and general program setup for the Reset and Interrupt Vector Addresses is:
When the BOOTRST Fuse is programmed, the Boot section size set to 8K bytes and the IVSEL
bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general
program setup for the Reset and Interrupt Vector Addresses is:
The General Interrupt Control Register controls the placement of the Interrupt Vector table.
Address Labels Code
.org 0x0002
0x0002
0x0004
:.
0x0044
;
.org 0x7000
0x7000 RESET: ldi
0x7001
0x7002
0x7003
0x7004
0x7005
Address Labels Code
;
.org 0x7000
0x7000
0x7002
0x7004
:.
0x7044
0x7046 RESET: ldi
0x7047
0x7048
0x7049
0x704A
0x704B
jmp
jmp
:.
jmp
out
ldi
out
sei
<instr>
jmp
jmp
jmp
:.
jmp
out
ldi
out
sei
<instr>
EXT_INT0 ; IRQ0 Handler
EXT_INT1 ; IRQ1 Handler
:.
SPM_RDY
r16,high(RAMEND); Main program start
SPH,r16
r16,low(RAMEND)
SPL,r16
RESET
EXT_INT0 ; IRQ0 Handler
EXT_INT1 ; IRQ1 Handler
:.
SPM_RDY ; Store Program Memory Ready Handler
r16,high(RAMEND); Main program start
SPH,r16
r16,low(RAMEND)
SPL,r16
xxx
xxx
;
; Store Program Memory Ready Handler
; Set Stack Pointer to top of RAM
; Enable interrupts
; Reset handler
;
; Set Stack Pointer to top of RAM
; Enable interrupts
Comments
Comments
ATmega64A
63

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