AT32UC3A3128-ALUT Atmel, AT32UC3A3128-ALUT Datasheet - Page 186
![IC MCU 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A3128-ALUT
Manufacturer Part Number
AT32UC3A3128-ALUT
Description
IC MCU 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A3128-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
110
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
IrDA/SCI/SCIF/UDI
Maximum Clock Frequency
66 MHz
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3128-ALUT
Manufacturer:
Atmel
Quantity:
135
- Current page: 186 of 1014
- Download datasheet (16Mb)
15.6.4.3
15.6.4.4
32072C–AVR32–2010/03
Write waveforms
NCS waveforms
•NWE waveforms
Figure 15-10. READMODE = 0: Data Is Sampled by SMC Before the Rising Edge of NCS
The write protocol is similar to the read protocol. It is depicted in
write cycle starts with the address setting on the memory address bus.
The NWE signal is characterized by a setup timing, a pulse width and a hold timing.
The NWE waveforms apply to all byte-write lines in byte write access mode: NWR0 to NWR3.
The NCS signal waveforms in write operation are not the same that those applied in read opera-
tions, but are separately defined.
1. NWESETUP: the NWE setup time is defined as the setup of address and data before
2. NWEPULSE: the NWE pulse length is the time between NWE falling edge and NWE
3. NWEHOLD: the NWE hold time is defined as the hold time of address and data after
1. NCSWRSETUP: the NCS setup time is defined as the setup time of address before the
2. NCSWRPULSE: the NCS pulse length is the time between NCS falling edge and NCS
3. NCSWRHOLD: the NCS hold time is defined as the hold time of address after the NCS
A[AD_MSB:2]
NBS0, NBS1,
the NWE falling edge.
rising edge.
the NWE rising edge.
NCS falling edge.
rising edge;
rising edge.
A0, A1
CLK_SMC
D[15:0]
NRD
NCS
t
PACC
Data Sampling
Figure 15-11 on page
AT32UC3A3/A4
187. The
Page
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