AT32UC3A3128-ALUT Atmel, AT32UC3A3128-ALUT Datasheet - Page 81
![IC MCU 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A3128-ALUT
Manufacturer Part Number
AT32UC3A3128-ALUT
Description
IC MCU 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A3128-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
110
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
IrDA/SCI/SCIF/UDI
Maximum Clock Frequency
66 MHz
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3128-ALUT
Manufacturer:
Atmel
Quantity:
135
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8.5.1.3
8.5.1.4
8.5.1.5
32072C–AVR32–2010/03
RTC interrupt
RTC wakeup
Busy bit
The RTC count value can be read from or written to the Value register (VAL). Due to synchroni-
zation, continuous reading of the VAL register with the lowest prescaler setting will skip every
other value.
The RTC interrupt is enabled by writing a one to the Top Interrupt bit in the Interrupt Enable Reg-
ister (IER.TOPI), and is disabled by writing a one to the Top Interrupt bit in the Interrupt Disable
Register (IDR.TOPI). The Interrupt Mask Register (IMR) can be read to see whether or not the
interrupt is enabled. If enabled, an interrupt will be generated if the TOPI bit in the Interrupt Sta-
tus Register (ISR) is set. The TOPI bit in ISR can be cleared by writing a one to the TOPI bit in
the Interrupt Clear Register (ICR.TOPI).
The RTC interrupt can wake the CPU from all sleep modes except DeepStop and Static modes.
The RTC can also wake up the CPU directly without triggering an interrupt when the ISR.TOPI
bit is set. In this case, the CPU will continue executing from the instruction following the sleep
instruction.
This direct RTC wake-up is enabled by writing a one to the Wake Enable bit in the CTRL register
(CTRL.WAKEN). When the CPU wakes from sleep, the CTRL.WAKEN bit must be written to
zero to clear the internal wake signal to the sleep controller, otherwise a new sleep instruction
will have no effect.
The RTC wakeup is available in all sleep modes except Static mode. The RTC wakeup can be
configured independently of the RTC interrupt.
Due to the crossing of clock domains, the RTC uses a few clock cycles to propagate the values
stored in CTRL, TOP, and VAL to the RTC. The RTC Busy bit in CTRL (CTRL.BUSY) indicates
that a register write is still going on and all writes to TOP, CTRL, and VAL will be discarded until
the CTRL.BUSY bit goes low again.
AT32UC3A3/A4
81
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