AT32UC3A3128-ALUT Atmel, AT32UC3A3128-ALUT Datasheet - Page 515
![IC MCU 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A3128-ALUT
Manufacturer Part Number
AT32UC3A3128-ALUT
Description
IC MCU 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A3128-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
110
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
IrDA/SCI/SCIF/UDI
Maximum Clock Frequency
66 MHz
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3128-ALUT
Manufacturer:
Atmel
Quantity:
135
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Figure 24-13. Transmit and Receive Frame Format in Edge/Pulse Start Modes
32072C–AVR32–2010/03
RX_FRAME_SYNC
TX_FRAME_SYNC
(If FSDEN = 1)
(If FSDEN = 0)
RX_DATA
TX_DATA
TX_DATA
/
Start
(1)
Table 24-3.
Note:
Figure 24-14. Transmit Frame Format in Continuous Mode
Note:
Transmitter
From TSHR
Sync Data
Sync Data
To RSHR
TFMR
TFMR
TFMR
TFMR
TFMR
TFMR
FSLEN
Example of input on falling edge of TX_FRAME_SYNC/RX_FRAME_SYNC.
STTDLY is written to zero. In this example, THR is loaded twice. FSDEN value has no effect on the
transmission. SyncData cannot be output in continuous mode.
From DATDEF
STTDLY
Default
Data Framing Format Registers
From DATDEF
Receiver
Default
Ignored
RFMR
RFMR
RFMR
RFMR
TX_DATA
Start: 1. TXEMPTY set to one
{FSLENHI,FSLEN}
From THR
2. Write into the THR
From THR
DATLEN
Start
To RHR
Bit/Field
DATLEN
DATDEF
Data
Data
Data
FSDEN
PERIOD
DATNB
MSBF
From THR
DATLEN
Data
DATNB
From THR
Up to 256
From THR
DATLEN
Up to 16
Up to 32
Length
From THR
DATLEN
To RHR
Data
Data
Data
Data
Number of words transmitted in
frame
Size of word
Size of Synchro data register
Most significant bit first
Enable send TSHR
Data default value ended
From DATDEF
Default
Ignored
Default
AT32UC3A3/A4
Start
From DATDEF
Comment
Default
Sync Data
Sync Data
515
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