AT32UC3A3128-ALUT Atmel, AT32UC3A3128-ALUT Datasheet - Page 999
![IC MCU 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A3128-ALUT
Manufacturer Part Number
AT32UC3A3128-ALUT
Description
IC MCU 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A3128-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
110
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
IrDA/SCI/SCIF/UDI
Maximum Clock Frequency
66 MHz
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3128-ALUT
Manufacturer:
Atmel
Quantity:
135
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38.2.5
38.2.6
32072C–AVR32–2010/03
SPI
USART
1. SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and
2. SPI Disable does not work in Slave mode
3. SPI RDR.PCS is not correct
4. SPI data transfer hangs with CSAAT=1 in CSR0 and MODFDIS=0 in MR
5. Disabling SPI has no effect on the TDRE flag
1. The NER register always returns zero.
2. USART - RTS output signal does not function properly in hardware handshaking
Activate the sleep mode in the mode register and then perform an AD conversion.
NCPHA=0
When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't
equal to 1, and CPOL=1 and CPHA=0, then an additional pulse will be generated on SCK.
Fix/workaround
When multiple CS are in use, if one of the baudrate equals 1, the other must
also equal 1 if CPOL=1 and CPHA=0.
Fix/workaround
Read the last received data then perform a Software reset.
The PCS (Peripheral Chip Select) field in the SPI RDR (Receive Data Register) does not
correctly indicate the value on the NPCS pins at the end of a transfer.
Fix/Workaround
Do not use the PCS field of the SPI RDR.
When CSAAT=1 in CSR0 and mode fault detection is enabled (MODFDIS=0 in MR), the
SPI module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MODFDIS in MR.
Disabling SPI has no effect on TDRE whereas the write data command is filtered when SPI
is disabled. This means that as soon as the SPI is disabled it becomes impossible to reset
the TDRE flag by writing in the TDR. So if the SPI is disabled during a PDCA transfer, the
PDCA will continue to write data in the TDR (as TDRE stays high) until its buffer is empty,
and all data written after the disable command is lost.
Fix/Workaround
Disable the PDCA, 2 NOP (minimum), disable SPI. When you want to continue the transfer:
Enable SPI, enable PDCA.
Fix/Workaround
None.
mode
The RTS signal is not generated properly when the USART receives data in hardware hand-
shaking mode. When the Peripheral DMA receive buffer becomes full, the RTS output
should go high, but it will stay low.
Fix/Workaround
Do not use the hardware handshaking mode of the USART. If it is necessary to drive the
RTS output high when the Peripheral DMA receive buffer becomes full, use the normal
mode of the USART. Configure the Peripheral DMA Controller to signal an interrupt when
the receive buffer is full. In the interrupt handler code, write a one to the RTSDIS bit in the
AT32UC3A3/A4
999
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