AT32UC3A3128-ALUT Atmel, AT32UC3A3128-ALUT Datasheet - Page 841
![IC MCU 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A3128-ALUT
Manufacturer Part Number
AT32UC3A3128-ALUT
Description
IC MCU 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A3128-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
110
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
IrDA/SCI/SCIF/UDI
Maximum Clock Frequency
66 MHz
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3128-ALUT
Manufacturer:
Atmel
Quantity:
135
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30.6.5.2
30.6.6
30.6.6.1
30.6.6.2
30.6.6.3
32072C–AVR32–2010/03
CE-ATA Operation
SDIO Interrupts
Executing an ATA Polling Command
Executing an ATA Interrupt Command
Aborting an ATA Command
An SDIO Card can have multiple I/O or combined I/O and memory (called Combo Card). Within
a multi-function SDIO or a Combo card, there are multiple devices (I/O and memory) that share
access to the SD bus. In order to allow the sharing of access to the host among multiple devices,
SDIO and combo cards can implement the optional concept of suspend/resume (Refer to the
SDIO Specification for more details). To send a suspend or a resume command, the host must
set the SDIO Special Command field in CMDR register (CMDR.IOSPCMD).
Each function within an SDIO or Combo card may implement interrupts (Refer to the SDIO
Specification for more details). In order to allow the SDIO card to interrupt the host, an interrupt
function is added to a pin on the DAT[1] line to signal the card’s interrupt to the host. An SDIO
interrupt on each slot can be enabled in the IER register. The SDIO interrupt is sampled regard-
less of the currently selected slot.
CE-ATA maps the streamlined ATA command set onto the MMC interface. The ATA task file is
mapped onto MMC register space.
CE-ATA utilizes five MMC commands:
CE-ATA utilizes the same MMC command sequences for initialization as traditional MMC
devices.
If the host needs to abort an ATA command prior to the completion signal it must send a special
command to avoid potential collision on the command line. The Special Command field of
• GO_IDLE_STATE (CMD0): used for hard reset.
• STOP_TRANSMISSION (CMD12): causes the ATA command currently executing to be
• FAST_IO (CMD39): Used for single register access to the ATA taskfile registers, eight bit
• RW_MULTIPLE_REGISTERS (CMD60): used to issue an ATA command or to access the
• RW_MULTIPLE_BLOCK (CMD61): used to transfer data for an ATA command.
1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for eight kB of
2. Read the ATA status register until DRQ is set.
3. Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA.
4. Read the ATA status register until DRQ && BSY are set to 0.
1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for eight kB of
2. Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA.
3. Wait for Completion Signal Received Interrupt.
aborted.
access only.
control/status registers.
DATA.
DATA with the IEN field written to zero to enable the command completion signal in the
device.
AT32UC3A3/A4
841
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