AT32UC3A3128-ALUT Atmel, AT32UC3A3128-ALUT Datasheet - Page 344
![IC MCU 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A3128-ALUT
Manufacturer Part Number
AT32UC3A3128-ALUT
Description
IC MCU 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A3128-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
110
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
IrDA/SCI/SCIF/UDI
Maximum Clock Frequency
66 MHz
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3128-ALUT
Manufacturer:
Atmel
Quantity:
135
- Current page: 344 of 1014
- Download datasheet (16Mb)
19.11.1
32072C–AVR32–2010/03
Abnormal Transfer Termination
When CTLx.SRC_TR_WIDTH is less than CTLx.DST_TR_WIDTH and the CFGx.CH_SUSP bit
is high, the CFGx.FIFO_EMPTY is asserted once the contents of the FIFO do not permit a single
word of CTLx.DST_TR_WIDTH to be formed. However, there may still be data in the channel
FIFO but not enough to form a single transfer of CTLx.DST_TR_WIDTH width. In this configura-
tion, once the channel is disabled, the remaining data in the channel FIFO are not transferred to
the destination peripheral. It is permitted to remove the channel from the suspension state by
writing a ‘0’ to the CFGx.CH_SUSP register. The DMA transfer completes in the normal manner.
Note:
A DMACA DMA transfer may be terminated abruptly by software by clearing the channel enable
bit, ChEnReg.CH_EN. This does not mean that the channel is disabled immediately after the
ChEnReg.CH_EN bit is cleared over the HSB slave interface. Consider this as a request to dis-
able the channel. The ChEnReg.CH_EN must be polled and then it must be confirmed that the
channel is disabled by reading back 0. A case where the channel is not be disabled after a chan-
nel disable request is where either the source or destination has received a split or retry
response. The DMACA must keep re-attempting the transfer to the system HADDR that origi-
nally received the split or retry response until an OKAY response is returned. To do otherwise is
an System Bus protocol violation.
Software may terminate all channels abruptly by clearing the global enable bit in the DMACA
Configuration Register (DmaCfgReg[0]). Again, this does not mean that all channels are dis-
abled immediately after the DmaCfgReg[0] is cleared over the HSB slave interface. Consider
this as a request to disable all channels. The ChEnReg must be polled and then it must be con-
firmed that all channels are disabled by reading back ‘0’.
Note:
Note:
3. The ChEnReg.CH_EN bit can then be cleared by software once the channel FIFO is
empty.
If a channel is disabled by software, an active single or burst transaction is not guaranteed to
receive an acknowledgement.
If the channel enable bit is cleared while there is data in the channel FIFO, this data is not sent to
the destination peripheral and is not present when the channel is re-enabled. For read sensitive
source peripherals such as a source FIFO this data is therefore lost. When the source is not a
read sensitive device (i.e., memory), disabling a channel without waiting for the channel FIFO to
empty may be acceptable as the data is available from the source peripheral upon request and is
not lost.
If a channel is disabled by software, an active single or burst transaction is not guaranteed to
receive an acknowledgement.
AT32UC3A3/A4
344
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