AT91SAM7SE32-AU Atmel, AT91SAM7SE32-AU Datasheet - Page 132
![MCU ARM 32K HS FLASH 128-LQFP](/photos/6/71/67112/128-lqfp_sml.jpg)
AT91SAM7SE32-AU
Manufacturer Part Number
AT91SAM7SE32-AU
Description
MCU ARM 32K HS FLASH 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7SE32-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Controller Family/series
AT91SAM7xxxx
No. Of I/o's
88
Ram Memory Size
8KB
Cpu Speed
48MHz
No. Of Timers
3
Rohs Compliant
Yes
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
EBI, SPI, TWI, USART
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
88
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7SE32-AU
Manufacturer:
ATMEL
Quantity:
624
Part Number:
AT91SAM7SE32-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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20.3.3
20.3.4
132
AT91SAM7SE512/256/32 Preliminary
Read/Write Handshake
Device Operations
The read/write handshake is done by carrying out read/write operations on two registers of the
device that are accessible through the JTAG:
Access to these registers is done through the TAP 38-bit DR register comprising a 32-bit data
field, a 5-bit address field and a read/write bit. The data to be written is scanned into the 32-bit
data field with the address of the register to the 5-bit address field and 1 to the read/write bit. A
register is read by scanning its address into the address field and 0 into the read/write bit, going
through the UPDATE-DR TAP state, then scanning out the data.
Refer to the ARM7TDMI reference manuel for more information on Comm channel operations.
Figure 20-5. TAP 8-bit DR Register
A read or write takes place when the TAP controller enters UPDATE-DR state. Refer to the IEEE
1149.1 for more details on JTAG operations.
The write handshake is done by polling the Debug Comms Control Register until the R bit is
cleared. Once cleared, data can be written to the Debug Comms Data Register.
The read handshake is done by polling the Debug Comms Control Register until the W bit is set.
Once set, data can be read in the Debug Comms Data Register.
Several commands on the Flash memory are available. These commands are summarized in
Table 20-3 on page
is reading and writing the Debug Comms Registers.
TDI
• Debug Comms Control Register: DCCR
• Debug Comms Data Register: DCDR
• The address of the Debug Comms Control Register is 0x04.
• The address of the Debug Comms Data Register is 0x05.
The Debug Comms Control Register is read-only and allows synchronized handshaking
between the processor and the debugger.
– Bit 1 (W): Denotes whether the programmer can read a data through the Debug
– Bit 0 (R): Denotes whether the programmer can send data from the Debug Comms
Comms Data Register. If the device is busy W = 0, then the programmer must poll
until W = 1.
Data Register. If R = 1, data previously placed there through the scan chain has not
been collected by the device and so the programmer must wait.
r/w
4
Address
Address
Decoder
122. Commands are run by the programmer through the serial interface that
5
0
31
Debug Comms Control Register
Debug Comms Data Register
Data
32
6222B–ATARM–26-Mar-07
0
TDO
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