AT91SAM7SE32-AU Atmel, AT91SAM7SE32-AU Datasheet - Page 642

• Manufacturer Part Number: AT91SAM7SE32-AU
• Description: MCU ARM 32K HS FLASH 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE32-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Controller Family/series: AT91SAM7xxxx
• No. Of I/o's: 88
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: EBI, SPI, TWI, USART
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

43.2
43.2.1
43.2.1.1
43.2.1.2
43.2.1.3
43.2.1.4
43.2.2
43.2.2.1
43.2.3
43.2.3.1
642
AT91SAM7SE512/256/32 Errata - Rev. A Parts
AT91SAM7SE512/256/32 Preliminary
Pulse Width Modulation Controller (PWM)
Real-Time Timer (RTT)
Serial Peripheral Interface (SPI)
PWM: Update when PWM_CCNTx = 0 or 1
PWM: Update when PWM_CPRDx = 0
PWM: Counter Start Value
PWM: Behavior of CHIDx Status Bits in the PWM_SR Register
RTT: Possible Event Loss when Reading RTT_SR
SPI: Baudrate Set to 1
Refer to
If the Channel Counter Register value is 0 or 1, the Channel Period Register or Channel Duty
Cycle Register is directly modified when writing the Channel Update Register.
Check the Channel Counter Register before writing the Channel Update Register.
When the Channel Period Register equals 0, the period update is not operational.
Do not write 0 in the Channel Period Register.
In left aligned mode, the first start value of the counter is 0. For the other periods, the counter
starts at 1.
None.
Erratic behavior of the CHIDx status bit in the PWM_SR Register. When a channel is disabled
by writing in the PWM_DIS Register just after enabling it (before completion of a Clock Period of
the clock selected for the channel), the PWM line is internally disabled but the CHIDx status bit
in the PWM_SR stays at 1.
Do not disable a channel before completion of one period of the selected clock.
If an event (RTTINC or ALMS) occurs within the same slow clock cycle that RTT_SR is read, the
corresponding bit might be cleared. This might lead to the loss of this event.
The software must handle RTT event as interrupt and should not poll RTT_SR.
When the Baudrate is set at 1 (so, the serial clock frequency equals the master clock), and when
the BITS field (number of bits to be transmitted) in SPI_CSRx equals an odd value (in this case
9, 11, 13 or 15), an additional pulse will be generated on SPCK.
It does not occur when the BITS field is equal to 8, 10, 12, 14 or 16 and the Baudrate is equal
to 1.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Section 43.1 ”Marking” on page
641.
6222B–ATARM–26-Mar-07