AT91SAM7SE32-AU Atmel, AT91SAM7SE32-AU Datasheet - Page 394

• Manufacturer Part Number: AT91SAM7SE32-AU
• Description: MCU ARM 32K HS FLASH 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE32-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Controller Family/series: AT91SAM7xxxx
• No. Of I/o's: 88
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: EBI, SPI, TWI, USART
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

33.9.7
33.9.7.1
Figure 33-22. Repeated Start + Reversal from Read to Write Mode
Note:
33.9.7.2
Figure 33-23. Repeated Start + Reversal from Write to Read Mode
Notes:
394
TWI_RHR
TWI_RHR
TWI_THR
TWI_THR
TXCOMP
EOSACC
TXCOMP
SVREAD
EOSACC
SVREAD
RXRDY
RXRDY
SVACC
SVACC
TXRDY
TXRDY
TWD
TWD
1. 1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.
1. In this case, if TWI_THR has not been written at the end of the read command, the clock is automatically stretched before
2. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.
AT91SAM7SE512/256/32 Preliminary
Reversal after a Repeated Start
the ACK.
Reversal of Read to Write
Reversal of Write to Read
S
S
As soon as a START is detected
As soon as a START is detected
SADR
SADR
The master initiates the communication by a read command and finishes it by a write command.
Figure 33-22
The master initiates the communication by a write command and finishes it by a read command.
Figure 33-23
W
R
Read TWI_RHR
A
A
DATA0
DATA0
DATA0
describes the repeated start + reversal from Read to Write mode.
describes the repeated start + reversal from Write to Read mode.
A
A
DATA0
DATA1
DATA1
DATA1
NA
A
DATA1
RS
RS
SADR
SADR
Cleared after read
Cleared after read
W
R
DATA2
A
A
DATA2
DATA2
DATA2
A
A
DATA3
DATA3
DATA3
6222B–ATARM–26-Mar-07
DATA3
NA
A
P
P