AT91SAM7SE32-AU Atmel, AT91SAM7SE32-AU Datasheet - Page 517

• Manufacturer Part Number: AT91SAM7SE32-AU
• Description: MCU ARM 32K HS FLASH 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE32-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Controller Family/series: AT91SAM7xxxx
• No. Of I/o's: 88
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: EBI, SPI, TWI, USART
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

36.6.6
Register Name:
Access Type:
• TCCLKS: Clock Selection
• CLKI: Clock Invert
0 = Counter is incremented on rising edge of the clock.
1 = Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
• LDBSTOP: Counter Clock Stopped with RB Loading
0 = Counter clock is not stopped when RB loading occurs.
1 = Counter clock is stopped when RB loading occurs.
• LDBDIS: Counter Clock Disable with RB Loading
0 = Counter clock is not disabled when RB loading occurs.
1 = Counter clock is disabled when RB loading occurs.
6222B–ATARM–26-Mar-07
WAVE = 0
LDBDIS
31
23
15
–
–
7
0
0
0
0
1
1
1
1
0
0
1
1
TC Channel Mode Register: Capture Mode
BURST
LDBSTOP
CPCTRG
30
22
14
TC_CMR
Read/Write
–
–
6
TCCLKS
0
1
0
1
0
0
1
1
0
0
1
1
The clock is not gated by an external signal.
XC0 is ANDed with the selected clock.
XC1 is ANDed with the selected clock.
XC2 is ANDed with the selected clock.
29
21
13
–
–
–
5
BURST
0
1
0
1
0
1
0
1
AT91SAM7SE512/256/32 Preliminary
28
20
12
–
–
–
4
Clock Selected
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
CLKI
27
19
11
–
–
3
LDRB
ABETRG
26
18
10
–
2
TCCLKS
25
17
–
9
1
ETRGEDG
LDRA
24
16
–
8
0
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