AT91SAM7SE32-AU Atmel, AT91SAM7SE32-AU Datasheet - Page 173

• Manufacturer Part Number: AT91SAM7SE32-AU
• Description: MCU ARM 32K HS FLASH 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE32-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Controller Family/series: AT91SAM7xxxx
• No. Of I/o's: 88
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: EBI, SPI, TWI, USART
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 22-14. NWAIT Behavior in Read Access [NWS = 3]
Notes:
Figure 22-15. NWAIT Behavior in Write Access [NWS = 3]
22.6.4.3
6222B–ATARM–26-Mar-07
internally synchronized
internally synchronized
1. Early Read Protocol
2. Standard Read Protocol
Data Float Wait States
NWAIT
NWAIT
D[15:0]
A[22:0]
NWE
MCK
A[22:0]
NWAIT
NWAIT
MCK
NRD
NCS
Some memory devices are slow to release the external bus. For such devices, it is necessary to
add wait states (data float wait states) after a read access before starting a write access or a
read access to a different external memory.
The Data Float Output Time (t
field of the SMC_CSR register for the corresponding chip select
on page
Wait Delay from NRD
(1)
Wait Delay
from NWE
198). The value of TDF indicates the number of data float wait cycles (between 0 and
(2)
Synchronization Delay
Synchronization Delay
AT91SAM7SE512/256/32 Preliminary
NWAIT
NWAIT
DF
) for each external memory device is programmed in the TDF
(”SMC Chip Select Registers”
173