AT91SAM7SE32-AU Atmel, AT91SAM7SE32-AU Datasheet - Page 381

• Manufacturer Part Number: AT91SAM7SE32-AU
• Description: MCU ARM 32K HS FLASH 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE32-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Controller Family/series: AT91SAM7xxxx
• No. Of I/o's: 88
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: EBI, SPI, TWI, USART
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 33-6. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Figure 33-7. Master Write with One Byte Internal Address and Multiple Data Bytes
6222B–ATARM–26-Mar-07
TXCOMP
TWD
TWD
TWD
TXRDY
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
S
S
S
S
Write THR
Write THR
DADR
DADR
DADR
DADR
The read sequence begins by setting the START bit. When the RXRDY bit is set in the status
register, a character has been received in the receive-holding register (TWI_RHR). The RXRDY
bit is reset when reading the TWI_RHR.
The TWI interface performs various transfer formats (7-bit slave address, 10-bit slave address).
The three internal address bytes are configurable through the Master Mode register
(TWI_MMR). If the slave device supports only a 7-bit address, the IADRSZ must be set to 0. For
slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the
other slave address bits in the internal address register (TWI_IADR).
Example: Address a 10-bit device
(10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10):
W
1. Program IADRSZ = 1,
2. Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.)
3. Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit
W
W
W
address)
A
A
A
A
IADR(7:0)
IADR(23:16)
IADR(15:8)
IADR(7:0)
A
AT91SAM7SE512/256/32 Preliminary
A
A
A
DATA
IADR(15:8)
IADR(7:0)
DATA
Write THR
A
A
A
A
IADR(7:0)
P
DATA
DATA
Write THR
A
A
A
P
DATA
DATA
A
A
P
P
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