AT91SAM7X512-AU Atmel, AT91SAM7X512-AU Datasheet - Page 105

• Manufacturer Part Number: AT91SAM7X512-AU
• Description: MCU ARM 512K HS FLASH 100-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X512-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: CAN, SPI, SSC, TWI, USART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7X-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• No. Of I/o's: 62
• Ram Memory Size: 128KB
• Cpu Speed: 55MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 4
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 19-2. Code Read Optimization in Thumb Mode for FWS = 0
Note:
Figure 19-3. Code Read Optimization in Thumb Mode for FWS = 1
Note:
6120H–ATARM–17-Feb-09
ARM Request (16-bit)
ARM Request (16-bit)
Data To ARM
Data To ARM
Buffer (32 bits)
Flash Access
Buffer (32 bits)
Flash Access
Master Clock
Master Clock
Code Fetch
When FWS is equal to 0, all accesses are performed in a single-cycle access.
When FWS is equal to 1, in case of sequential reads, all the accesses are performed in a single-cycle access (except for the
first one).
Code Fetch
@Byte 0
@Byte 0
1 Wait State Cycle
Bytes 0-3
@Byte 2
Bytes 0-1
Bytes 0-3
@Byte 2
Bytes 4-7
@Byte 4
Bytes 0-3
Bytes 2-3
Bytes 0-1
1 Wait State Cycle
AT91SAM7X512/256/128 Preliminary
Bytes 4-5
@Byte 6
@Byte 4
Bytes 2-3
Bytes 4-7
Bytes 4-7
Bytes 0-3
Bytes 8-11
@Byte 8
@Byte 6
Bytes 6-7
Bytes 4-5
1 Wait State Cycle
@Byte 10
Bytes 8-9
@Byte 8
Bytes 6-7
Bytes 8-11
Bytes 8-11
Bytes 4-7
Bytes 12-15
Bytes 10-11
@Byte 10
@Byte 12
Bytes 8-9
1 Wait State Cycle
Bytes 12-13
Bytes 10-11
@Byte 12
@Byte 14
Bytes 12-15
Bytes 8-11
Bytes 12-15
Bytes 16-19
Bytes 12-13
Bytes 14-15
@Byte 14
@Byte 16
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