AT91SAM7X512-AU Atmel, AT91SAM7X512-AU Datasheet - Page 577

• Manufacturer Part Number: AT91SAM7X512-AU
• Description: MCU ARM 512K HS FLASH 100-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X512-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: CAN, SPI, SSC, TWI, USART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7X-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• No. Of I/o's: 62
• Ram Memory Size: 128KB
• Cpu Speed: 55MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 4
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

37.4.1.7
6120H–ATARM–17-Feb-09
Receiving Frames
When a frame is received and the receive circuits are enabled, the EMAC checks the address
and, in the following cases, the frame is written to system memory:
The register receive buffer queue pointer points to the next entry (see
and the EMAC uses this as the address in system memory to write the frame to. Once the frame
has been completely and successfully received and written to system memory, the EMAC then
updates the receive buffer descriptor entry with the reason for the address match and marks the
area as being owned by software. Once this is complete an interrupt receive complete is set.
Software is then responsible for handling the data in the buffer and then releasing the buffer by
writing the ownership bit back to 0.
If the EMAC is unable to write the data at a rate to match the incoming frame, then an interrupt
receive overrun is set. If there is no receive buffer available, i.e., the next buffer is still owned by
software, the interrupt receive buffer not available is set. If the frame is not successfully
received, a statistic register is incremented and the frame is discarded without informing
software.
8. Write to the transmit start bit in the network control register.
• if it matches one of the four specific address registers.
• if it matches the hash address function.
• if it is a broadcast address (0xFFFFFFFFFFFF) and broadcasts are allowed.
• if the EMAC is configured to copy all frames.
AT91SAM7X512/256/128 Preliminary
Table 37-1 on page
565)
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