AT91SAM7X512-AU Atmel, AT91SAM7X512-AU Datasheet - Page 549

MCU ARM 512K HS FLASH 100-LQFP

AT91SAM7X512-AU

Manufacturer Part Number
AT91SAM7X512-AU
Description
MCU ARM 512K HS FLASH 100-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet

Specifications of AT91SAM7X512-AU

Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
128 KB
Interface Type
CAN, SPI, SSC, TWI, USART, USB
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
13
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7X-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
No. Of I/o's
62
Ram Memory Size
128KB
Cpu Speed
55MHz
No. Of Timers
3
No. Of Pwm Channels
4
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Price
Part Number:
AT91SAM7X512-AU
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36.8.10
Name:
Access Type:
This register initializes several transfer requests at the same time.
• MBx: Transfer Request for Mailbox x
This flag clears the MRDY and MABT flags in the corresponding CAN_MSRx register.
When several mailboxes are requested to be transmitted simultaneously, they are transmitted in turn, starting with the mail-
box with the highest priority. If several mailboxes have the same priority, then the mailbox with the lowest number is sent
first (i.e., MB0 will be transferred before MB1).
• TIMRST: Timer Reset
Resets the internal timer counter. If the internal timer counter is frozen, this command automatically re-enables it. This
command is useful in Time Triggered mode.
6120H–ATARM–17-Feb-09
TIMRST
MB7
31
23
15
Receive with overwrite
7
Mailbox Object Type
CAN Transfer Command Register
Consumer
Producer
Transmit
Receive
MB6
30
22
14
CAN_TCR
Write-only
6
Description
It receives the next message.
This triggers a new reception.
Sends data prepared in the mailbox as soon as possible.
Sends a remote frame.
Sends data prepared in the mailbox after receiving a remote frame from a
consumer.
MB5
29
21
13
5
MB4
AT91SAM7X512/256/128 Preliminary
28
20
12
4
MB3
27
19
11
3
MB2
26
18
10
2
MB1
25
17
9
1
MB0
24
16
8
0
549

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