AT91SAM7X512-AU Atmel, AT91SAM7X512-AU Datasheet - Page 71

• Manufacturer Part Number: AT91SAM7X512-AU
• Description: MCU ARM 512K HS FLASH 100-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X512-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: CAN, SPI, SSC, TWI, USART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7X-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• No. Of I/o's: 62
• Ram Memory Size: 128KB
• Cpu Speed: 55MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 4
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.3.3
Register Name:
Access Type:
• URSTEN: User Reset Enable
0 = The detection of a low level on the pin NRST does not generate a User Reset.
1 = The detection of a low level on the pin NRST triggers a User Reset.
• URSTIEN: User Reset Interrupt Enable
0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq.
1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.
• BODIEN: Brownout Detection Interrupt Enable
0 = BODSTS bit in RSTC_SR at 1 has no effect on rstc_irq.
1 = BODSTS bit in RSTC_SR at 1 asserts rstc_irq.
• ERSTL: External Reset Length
This field defines the external reset length. The external reset is asserted during a time of 2
allows assertion duration to be programmed between 60 µs and 2 seconds.
• KEY: Password
Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
6120H–ATARM–17-Feb-09
31
23
15
–
–
7
–
Reset Controller Mode Register
30
22
14
RSTC_MR
Read-write
–
–
6
–
29
21
13
–
–
5
URSTIEN
AT91SAM7X512/256/128 Preliminary
28
20
12
–
–
4
KEY
27
19
11
–
3
–
26
18
10
–
2
–
ERSTL
(ERSTL+1)
25
17
–
9
1
–
Slow Clock cycles. This
URSTEN
BODIEN
24
16
8
0
71