LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 148

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
Table 122. LPC2420/60/68 pin description
UM10237_4
User manual
Symbol
P2[15]/CS3/
CAP2[1]/SCL1
P2[16]/CAS
P2[17]/RAS
P2[18]/
CLKOUT0
P2[19]/
CLKOUT1
P2[20]/DYCS0
P2[21]/DYCS1
P2[22]/DYCS2/
CAP3[0]/SCK0
P2[23]/DYCS3/
CAP3[1]/SSEL0
P2[24]/
CKEOUT0
P2[25]/
CKEOUT1
P2[26]/
CKEOUT2/
MAT3[0]/MISO0
P2[27]/
CKEOUT3/
MAT3[1]/MOSI0
P2[28]/
DQMOUT0
P2[29]/
DQMOUT1
Pin
99
87
95
59
67
73
81
85
64
53
54
57
47
49
43
[6]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
Ball
P13
R11
R13
U3
R7
T8
U11
U12
U5
P5
R4
T4
P3
P4
N3
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[6]
[1]
[1]
[1]
[1]
Type
I/O
O
I
I/O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I
I/O
I/O
O
I
I/O
I/O
O
I/O
O
I/O
O
O
I/O
I/O
O
O
I/O
I/O
O
I/O
O
…continued
Rev. 04 — 26 August 2009
Description
P2[15] — General purpose digital input/output pin.
CS3 — LOW active Chip Select 3 signal.
CAP2[1] — Capture input for Timer 2, channel 1.
SCL1 — I
P2[16] — General purpose digital input/output pin.
CAS — LOW active SDRAM Column Address Strobe.
P2[17] — General purpose digital input/output pin.
RAS — LOW active SDRAM Row Address Strobe.
P2[18] — General purpose digital input/output pin.
CLKOUT0 — SDRAM clock 0.
P2[19] — General purpose digital input/output pin.
CLKOUT1 — SDRAM clock 1.
P2[20] — General purpose digital input/output pin.
DYCS0 — SDRAM chip select 0.
P2[21] — General purpose digital input/output pin.
DYCS1 — SDRAM chip select 1.
P2[22] — General purpose digital input/output pin.
DYCS2 — SDRAM chip select 2.
CAP3[0] — Capture input for Timer 3, channel 0.
SCK0 — Serial clock for SSP0.
P2[23] — General purpose digital input/output pin.
DYCS3 — SDRAM chip select 3.
CAP3[1] — Capture input for Timer 3, channel 1.
SSEL0 — Slave Select for SSP0.
P2[24] — General purpose digital input/output pin.
CKEOUT0 — SDRAM clock enable 0.
P2[25] — General purpose digital input/output pin.
CKEOUT1 — SDRAM clock enable 1.
P2[26] — General purpose digital input/output pin.
CKEOUT2 — SDRAM clock enable 2.
MAT3[0] — Match output for Timer 3, channel 0.
MISO0 — Master In Slave Out for SSP0.
P2[27] — General purpose digital input/output pin.
CKEOUT3 — SDRAM clock enable 3.
MAT3[1] — Match output for Timer 3, channel 1.
MOSI0 — Master Out Slave In for SSP0.
P2[28] — General purpose digital input/output pin.
DQMOUT0 — Data mask 0 used with SDRAM and static devices.
P2[29] — General purpose digital input/output pin.
DQMOUT1 — Data mask 1 used with SDRAM and static devices.
2
C1 clock input/output (this is not an open-drain pin).
Chapter 8: LPC24XX Pin configuration
UM10237
© NXP B.V. 2009. All rights reserved.
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