LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 776
LPC2468FET208,551
Manufacturer Part Number
LPC2468FET208,551
Description
IC ARM7 MCU FLASH 512K 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2468FET208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2S/ISP/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
6
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
Development Tools By Supplier
OM10100
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4262
935283234551
LPC2468FET208-S
935283234551
LPC2468FET208-S
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Manufacturer
Quantity
Price
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Part Number:
LPC2468FET208,551
Manufacturer:
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Quantity:
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3.2.12
3.2.13
3.2.14
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.4
3.4.1
3.4.2
Chapter 5: LPC24XX External Memory Controller (EMC)
1
2
3
4
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.3
5.4
5.4.1
5.4.2
5.5
6
6.1
6.2
7
8
9
10
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
UM10237_4
User manual
How to read this chapter . . . . . . . . . . . . . . . . . 68
Basic configuration . . . . . . . . . . . . . . . . . . . . . 68
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
EMC functional description . . . . . . . . . . . . . . 69
Low-power operation. . . . . . . . . . . . . . . . . . . . 72
Memory bank select . . . . . . . . . . . . . . . . . . . . 73
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 74
Register description . . . . . . . . . . . . . . . . . . . . 75
Procedure for determining PLL settings . . . . . 54
Examples of PLL settings . . . . . . . . . . . . . . . . 55
PLL setup sequence . . . . . . . . . . . . . . . . . . . . 56
Clock dividers . . . . . . . . . . . . . . . . . . . . . . . . . 57
CPU Clock Configuration register (CCLKCFG -
0xE01F C104) . . . . . . . . . . . . . . . . . . . . . . . . 57
USB Clock Configuration register (USBCLKCFG -
0xE01F C108) . . . . . . . . . . . . . . . . . . . . . . . . 58
IRC Trim Register (IRCTRIM - 0xE01F C1A4) 58
Peripheral Clock Selection registers 0 and 1
(PCLKSEL0 - 0xE01F C1A8 and PCLKSEL1 -
0xE01F C1AC) . . . . . . . . . . . . . . . . . . . . . . . . 58
Power control . . . . . . . . . . . . . . . . . . . . . . . . . 60
Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 60
AHB slave register interface . . . . . . . . . . . . . . 70
AHB slave memory interface . . . . . . . . . . . . . 71
Memory transaction endianness. . . . . . . . . . . 71
Memory transaction size. . . . . . . . . . . . . . . . . 71
Write protected memory areas . . . . . . . . . . . . 71
Pad interface . . . . . . . . . . . . . . . . . . . . . . . . . 71
Data buffers . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Write buffers . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Read buffers . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Memory controller state machine . . . . . . . . . . 72
Low-power SDRAM Deep-sleep Mode. . . . . . 73
Low-power SDRAM partial array refresh . . . . 73
EMC Control register (EMCControl -
0xFFE0 8000) . . . . . . . . . . . . . . . . . . . . . . . . . 77
EMC Status register (EMCStatus -
0xFFE0 8004) . . . . . . . . . . . . . . . . . . . . . . . . . 78
EMC Configuration register (EMCConfig -
0xFFE0 8008) . . . . . . . . . . . . . . . . . . . . . . . . . 79
Dynamic Memory Control register
(EMCDynamicControl - 0xFFE0 8020) . . . . . . 79
Dynamic Memory Refresh Timer register
(EMCDynamicRefresh - 0xFFE0 8024) . . . . . 81
Dynamic Memory Read Configuration register
(EMCDynamicReadConfig - 0xFFE0 8028) . . 82
Dynamic Memory Percentage Command Period
register (EMCDynamictRP - 0xFFE0 8030) . . 82
Dynamic Memory Active to Precharge Command
Period register (EMCDynamictRAS -
0xFFE0 8034) . . . . . . . . . . . . . . . . . . . . . . . . . 83
Rev. 04 — 26 August 2009
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
3.4.10
4
5
10.9
10.10
10.11
10.12
10.13
10.14
10.15
10.16
10.17
10.18
10.19
10.20
10.21
10.22
10.23
Chapter 36: LPC24XX Supplementary information
Power domains . . . . . . . . . . . . . . . . . . . . . . . . 66
Wakeup timer. . . . . . . . . . . . . . . . . . . . . . . . . . 67
Power-down mode . . . . . . . . . . . . . . . . . . . . . 61
Deep power-down mode . . . . . . . . . . . . . . . . 61
Peripheral power control . . . . . . . . . . . . . . . . 62
Power control register description . . . . . . . . . 62
Power Mode Control register (PCON -
0xE01F C0C0) . . . . . . . . . . . . . . . . . . . . . . . . 62
Encoding of reduced power modes . . . . . . . . . 63
Interrupt Wakeup Register (INTWAKE -
0xE01F C144) . . . . . . . . . . . . . . . . . . . . . . . . 63
Power Control for Peripherals register (PCONP -
0xE01F C0C4) . . . . . . . . . . . . . . . . . . . . . . . . 65
Power control usage notes . . . . . . . . . . . . . . 66
Dynamic Memory Self-refresh Exit Time register
(EMCDynamictSREX - 0xFFE0 8038) . . . . . . 83
Dynamic Memory Last Data Out to Active Time
register (EMCDynamictAPR - 0xFFE0 803C) 84
Dynamic Memory Data-in to Active Command
Time register (EMCDynamictDAL -
0xFFE0 8040) . . . . . . . . . . . . . . . . . . . . . . . . 84
Dynamic Memory Write Recovery Time register
(EMCDynamictWR - 0xFFE0 8044). . . . . . . . 85
Dynamic Memory Active to Active Command
Period register (EMCDynamictRC -
0xFFE0 8048) . . . . . . . . . . . . . . . . . . . . . . . . 85
Dynamic Memory Auto-refresh Period register
(EMCDynamictRFC - 0xFFE0 804C). . . . . . . 86
Dynamic Memory Exit Self-refresh register
(EMCDynamictXSR - 0xFFE0 8050) . . . . . . . 86
Dynamic Memory Active Bank A to Active Bank B
Time register (EMCDynamictRRD -
0xFFE0 8054) . . . . . . . . . . . . . . . . . . . . . . . . 87
Dynamic Memory Load Mode register to Active
Command Time (EMCDynamictMRD -
0xFFE0 8058) . . . . . . . . . . . . . . . . . . . . . . . . 87
Static Memory Extended Wait register
(EMCStaticExtendedWait - 0xFFE0 8080). . . 88
Dynamic Memory Configuration registers
(EMCDynamicConfig0-3 - 0xFFE0 8100, 120,
140, 160) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Dynamic Memory RAS & CAS Delay registers
(EMCDynamicRASCAS0-3 - 0xFFE0 8104, 124,
144, 164) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Static Memory Configuration registers
(EMCStaticConfig0-3 - 0xFFE0 8200, 220, 240,
260) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Static Memory Write Enable Delay registers
(EMCStaticWaitWen0-3 - 0xFFE0 8204, 224, 244
,264). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Static Memory Output Enable Delay registers
(EMCStaticWaitOen0-3 - 0xFFE0 8208, 228, 248,
268) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
UM10237
© NXP B.V. 2009. All rights reserved.
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