LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 769
LPC2468FET208,551
Manufacturer Part Number
LPC2468FET208,551
Description
IC ARM7 MCU FLASH 512K 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2468FET208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2S/ISP/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
6
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
Development Tools By Supplier
OM10100
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4262
935283234551
LPC2468FET208-S
935283234551
LPC2468FET208-S
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Table 453.FullCAN Interrupt and Capture register 1
Table 454.Format of automatically stored Rx messages.509
Table 455.FullCAN semaphore operation . . . . . . . . . . . .509
Table 456.Example of Acceptance Filter Tables and ID index
Table 457.Used ID-Look-up Table sections. . . . . . . . . . .521
Table 458.Used ID-Look-up Table sections. . . . . . . . . . .522
Table 459.SPI Data To Clock Phase Relationship. . . . . .527
Table 460.SPI pin description . . . . . . . . . . . . . . . . . . . . .530
Table 461.SPI register map . . . . . . . . . . . . . . . . . . . . . . .531
Table 462:SPI Control Register (S0SPCR - address
Table 463:SPI Status Register (S0SPSR - address
Table 464:SPI Data Register (S0SPDR - address
Table 465:SPI Clock Counter Register (S0SPCCR - address
Table 466:SPI Test Control Register (SPTCR - address
Table 467:SPI Test Status Register (SPTSR - address
Table 468:SPI Interrupt Register (S0SPINT - address
Table 469.SSP pin descriptions . . . . . . . . . . . . . . . . . . .537
Table 470.SSP Register Map . . . . . . . . . . . . . . . . . . . . .545
Table 471:SSPn Control Register 0 (SSP0CR0 - address
Table 472:SSPn Control Register 1 (SSP0CR1 - address
Table 473:SSPn Data Register (SSP0DR - address
Table 474:SSPn Status Register (SSP0SR - address
Table 475:SSPn Clock Prescale Register (SSP0CPSR -
Table 476:SSPn Interrupt Mask Set/Clear register
Table 477:SSPn Raw Interrupt Status register (SSP0RIS -
Table 478:SSPn Masked Interrupt Status register (SSPnMIS
Table 479:SSPn interrupt Clear Register (SSP0ICR -
Table 480:SSPn DMA Control Register (SSP0DMACR -
UM10237_4
User manual
(FCANIC0 - address 0xE003 C024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .505
(FCANIC1 - address 0xE003 C028)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .505
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .519
0xE002 0000) bit description . . . . . . . . . . . . .531
0xE002 0004) bit description . . . . . . . . . . . . .532
0xE002 0008) bit description . . . . . . . . . . . . .533
0xE002 000C) bit description . . . . . . . . . . . . .533
0xE002 0010) bit description . . . . . . . . . . . . .534
0xE002 0014) bit description . . . . . . . . . . . . .534
0xE002 001C) bit description . . . . . . . . . . . . .534
0xE006 8000, SSP1CR0 - 0xE003 0000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .546
0xE006 8004, SSP1CR1 - 0xE003 0004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .547
0xE006 8008, SSP1DR - 0xE003 0008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .547
0xE006 800C, SSP1SR - 0xE003 000C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .548
address 0xE006 8010, SSP1CPSR -
0xE003 8010) bit description . . . . . . . . . . . . .548
(SSP0IMSC - address 0xE006 8014, SSP1IMSC
- 0xE003 0014) bit description . . . . . . . . . . . .549
address 0xE006 8018, SSP1RIS - 0xE003 0018)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .549
-address 0xE006 801C, SSP1MIS -
0xE003 001C) bit description . . . . . . . . . . . . .550
address 0xE006 8020, SSP1ICR - 0xE003 0020)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .550
Rev. 04 — 26 August 2009
Table 481.SD/MMC card interface pin description . . . . . 551
Table 482.Command format . . . . . . . . . . . . . . . . . . . . . . 556
Table 483.Simple response format . . . . . . . . . . . . . . . . . 556
Table 484.Long response format . . . . . . . . . . . . . . . . . . 556
Table 485.Command path status flags . . . . . . . . . . . . . . 557
Table 486.CRC token status . . . . . . . . . . . . . . . . . . . . . . 560
Table 487.Data path status flags . . . . . . . . . . . . . . . . . . 561
Table 488.Transmit FIFO status flags. . . . . . . . . . . . . . . 562
Table 489.Receive FIFO status flags . . . . . . . . . . . . . . . 563
Table 490.Summary of MCI registers . . . . . . . . . . . . . . . 563
Table 491:Power Control register (MCIPower - address
Table 492:Clock Control register (MCIClock - address
Table 493:Argument register (MCIArgument - address
Table 494:Command register (MCICommand - address
Table 495:Command Response Types. . . . . . . . . . . . . . 566
Table 496:Command Response register
Table 497:Response registers (MCIResponse0-3 -
Table 498:Response Register Type . . . . . . . . . . . . . . . . 567
Table 499:Data Timer register (MCIDataTimer - address
Table 500:Data Length register (MCIDataLength - address
Table 501:Data Control register (MCIDataCtrl - address
Table 502:Data Block Length . . . . . . . . . . . . . . . . . . . . . 568
Table 503:Data Counter register (MCIDataCnt - address
Table 504:Status register (MCIStatus - address
Table 505:Clear register (MCIClear - address 0xE008 C038)
Table 506:Interrupt Mask registers (MCIMask0 - address
Table 507:FIFO Counter register (MCIFifoCnt - address
Table 508:Data FIFO register (MCIFIFO - address
Table 509.I
Table 510.I2CnCONSET used to configure Master
Table 511. I2CnCONSET used to configure Slave mode 576
Table 512.Summary of I
Table 513.I
Table 514.I
Chapter 36: LPC24XX Supplementary information
address 0xE006 8024, SSP1DMACR -
0xE003 0024) bit description . . . . . . . . . . . . . 550
0xE008 C000) bit description. . . . . . . . . . . . . 564
0xE008 C004) bit description. . . . . . . . . . . . . 565
0xE008 C008) bit description. . . . . . . . . . . . . 565
0xE008 C00C) bit description . . . . . . . . . . . . 566
(MCIRespCommand - address 0xE008 C010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
addresses 0xE008 0014, 0xE008 C018,
0xE008 001C and 0xE008 C020) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
0xE008 C024) bit description. . . . . . . . . . . . . 567
0xE008 C028) bit description. . . . . . . . . . . . . 567
0xE008 C02C) bit description . . . . . . . . . . . . 568
0xE008 C030) bit description. . . . . . . . . . . . . 569
0xE008 C034) bit description. . . . . . . . . . . . . 569
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 570
0xE008 C03C) bit description . . . . . . . . . . . . 570
0xE008 C048) bit description. . . . . . . . . . . . . 571
0xE008 C080 to 0xE008 C0BC) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
addresses: 0xE001 C000, 0xE005 C000,
0xE008 0000) bit description . . . . . . . . . . . . . 582
2
2
2
C Pin Description. . . . . . . . . . . . . . . . . . . . . 574
C Control Set Register (I2C[0/1/2]CONSET -
C Control Set Register (I2C[0/1/2]CONCLR -
2
C registers. . . . . . . . . . . . . . . . 581
UM10237
© NXP B.V. 2009. All rights reserved.
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