LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 665
LPC2468FET208,551
Manufacturer Part Number
LPC2468FET208,551
Description
IC ARM7 MCU FLASH 512K 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2468FET208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2S/ISP/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
6
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
Development Tools By Supplier
OM10100
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4262
935283234551
LPC2468FET208-S
935283234551
LPC2468FET208-S
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Manufacturer:
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UM10237_4
User manual
4.4 Watchdog Timer Value Register (WDTV - 0xE000 000C)
4.5 Watchdog Timer Clock Source Selection Register (WDCLKSEL -
errors. After writing 0xAA to WDFEED, access to any Watchdog register other than writing
0x55 to WDFEED causes an immediate reset/interrupt when the Watchdog is enabled.
The reset will be generated during the second PCLK following an incorrect access to a
Watchdog register during a feed sequence.
Interrupts should be disabled during the feed sequence. An abort condition will occur if an
interrupt happens during the feed sequence.
Table 588: Watchdog Feed Register (WDFEED - address 0xE000 0008) bit description
The WDTV register is used to read the current value of Watchdog timer.
When reading the value of the 32 bit timer, the lock and synchronization procedure takes
up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the actual
value of the timer when it's being read by the CPU.
Table 589: Watchdog Timer Value register (WDTV - address 0xE000 000C) bit description
0xE000 0010)
This register allows selecting the clock source for the Watchdog timer. The possibilities are: the
Internal RC oscillator (IRC), the RTC oscillator, and the APB peripheral clock (pclk). The function of
bits in WDCLKSEL are shown in
Table 590: Watchdog Timer Clock Source Selection register (WDCLKSEL - address
Bit
7:0
Bit
31:0
Bit
1:0
31:2 -
Symbol Value Description
WDSEL
Symbol
Feed
Symbol
Count
0xE000 0010) bit description
00
01
10
11
-
Description
Feed value should be 0xAA followed by 0x55.
Description
Counter timer value.
These bits select the clock source for the Watchdog timer as
described below.
Warning: Improper setting of this value may result in incorrect
operation of the Watchdog timer, which could adversely affect
system operation.
Selects the Internal RC oscillator as the Watchdog clock source
(default).
Selects the APB peripheral clock (PCLK) as the Watchdog clock
source.
Selects the RTC oscillator as the Watchdog clock source.
Reserved
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Rev. 04 — 26 August 2009
Table 27–590
Chapter 27: LPC24XX WatchDog Timer (WDT)
.
UM10237
© NXP B.V. 2009. All rights reserved.
NA
0x0000 00FF
Reset Value
Reset Value
665 of 792
Reset
Value
0
NA
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