LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 788

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
10.10.2
10.10.3
Chapter 23: LPC24XX I
1
2
3
4
5
5.1
5.2
5.3
5.4
Chapter 24: LPC24XX Timer0/1/2/3
1
2
3
4
5
5.1
6
6.1
6.2
6.3
6.4
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
1
2
3
3.1
3.2
3.3
4
5
6
6.1
UM10237_4
User manual
Basic configuration . . . . . . . . . . . . . . . . . . . . 611
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . 612
Register description . . . . . . . . . . . . . . . . . . . 613
Basic configuration . . . . . . . . . . . . . . . . . . . . 621
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 621
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 622
Register description . . . . . . . . . . . . . . . . . . . 622
Basic configuration . . . . . . . . . . . . . . . . . . . . 632
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 637
PWM base addresses . . . . . . . . . . . . . . . . . . 637
Register description . . . . . . . . . . . . . . . . . . . 637
State : 0xB0 . . . . . . . . . . . . . . . . . . . . . . . . . 609
State : 0xB8 . . . . . . . . . . . . . . . . . . . . . . . . . 609
Digital Audio Output Register (I2SDAO -
0xE008 8000) . . . . . . . . . . . . . . . . . . . . . . . . 614
Digital Audio Input Register (I2SDAI -
0xE008 8004) . . . . . . . . . . . . . . . . . . . . . . . . 614
Transmit FIFO Register (I2STXFIFO -
0xE008 8008) . . . . . . . . . . . . . . . . . . . . . . . . 615
Receive FIFO Register (I2SRXFIFO -
0xE008 800C). . . . . . . . . . . . . . . . . . . . . . . . 615
Multiple CAP and MAT pins . . . . . . . . . . . . . 622
Interrupt Register (T[0/1/2/3]IR - 0xE000 4000,
0xE000 8000, 0xE007 0000, 0xE007 4000) . 624
Timer Control Register (T[0/1/2/3]CR -
0xE000 4004, 0xE000 8004, 0xE007 0004,
0xE007 4004) . . . . . . . . . . . . . . . . . . . . . . . . 624
Count Control Register (T[0/1/2/3]CTCR -
0xE000 4070, 0xE000 8070, 0xE007 0070,
0xE007 4070) . . . . . . . . . . . . . . . . . . . . . . . . 625
Timer Counter . . . . . . . .registers (T0TC - T3TC,
0xE000 4008, 0xE000 8008, 0xE007 0008,
0xE007 4008) . . . . . . . . . . . . . . . . . . . . . . . . 626
Rules for single edge controlled PWM
outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Rules for double edge controlled PWM
outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Summary of differences from the standard timer
block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
PWM Interrupt Register (PWM0IR - 0xE001 4000
and PWM1IR 0xE001 8000) . . . . . . . . . . . . . 639
2
S interface
Rev. 04 — 26 August 2009
10.10.4
10.10.5
5.5
5.6
5.7
5.8
5.9
5.10
6
7
6.5
6.6
6.7
6.8
6.9
6.10
6.11
7
8
6.2
6.3
6.4
6.5
6.6
6.7
Chapter 36: LPC24XX Supplementary information
I
FIFO controller . . . . . . . . . . . . . . . . . . . . . . . 618
Example timer operation . . . . . . . . . . . . . . . 630
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 630
2
S transmit and receive interfaces . . . . . . . 617
State : 0xC0 . . . . . . . . . . . . . . . . . . . . . . . . . 609
State : 0xC8 . . . . . . . . . . . . . . . . . . . . . . . . . 610
Status Feedback Register (I2SSTATE -
0xE008 8010). . . . . . . . . . . . . . . . . . . . . . . . 615
DMA Configuration Register 1 (I2SDMA1 -
0xE008 8014). . . . . . . . . . . . . . . . . . . . . . . . 616
DMA Configuration Register 2 (I2SDMA2 -
0xE008 8018). . . . . . . . . . . . . . . . . . . . . . . . 616
Interrupt Request Control Register (I2SIRQ -
0xE008 801C) . . . . . . . . . . . . . . . . . . . . . . . 616
Transmit Clock Rate Register (I2STXRATE -
0xE008 8020). . . . . . . . . . . . . . . . . . . . . . . . 617
Receive Clock Rate Register (I2SRXRATE -
0xE008 8024). . . . . . . . . . . . . . . . . . . . . . . . 617
Prescale register (T0PR - T3PR, 0xE000 400C,
0xE000 800C, 0xE007 000C, 0xE007 400C) 626
Prescale Counter register (T0PC - T3PC,
0xE000 4010, 0xE000 8010, 0xE007 0010,
0xE007 4010). . . . . . . . . . . . . . . . . . . . . . . . 626
Match Registers (MR0 - MR3) . . . . . . . . . . . 626
Match Control Register (T[0/1/2/3]MCR -
0xE000 4014, 0xE000 8014, 0xE007 0014,
0xE007 4014). . . . . . . . . . . . . . . . . . . . . . . . 627
Capture Registers (CR0 - CR3) . . . . . . . . . . 628
Capture Control Register (T[0/1/2/3]CCR -
0xE000 4028, 0xE000 8028, 0xE007 0028,
0xE007 4028). . . . . . . . . . . . . . . . . . . . . . . . 628
External Match Register (T[0/1/2/3]EMR -
0xE000 403C, 0xE000 803C, 0xE007 003C,
0xE007 403C) . . . . . . . . . . . . . . . . . . . . . . . 629
PWM Timer Control Register (PWM0TCR -
0xE001 4004 and PWM1TCR 0xE001 8004) 640
PWM Count Control Register (PWM0CTCR -
0xE001 4070 and PWM1CTCR
0xE001 8070). . . . . . . . . . . . . . . . . . . . . . . . 641
PWM Match Control Register (PWM0MCR -
0xE001 4014 and PWM1MCR 0xE001 8014) 641
PWM Capture Control Register (PWM0CCR -
0xE001 4028 and PWM1CCR 0xE001 8028) 643
PWM Control Registers (PWM0PCR -
0xE001 404C and PWM1PCR
0xE001 804C) . . . . . . . . . . . . . . . . . . . . . . . 644
PWM Latch Enable Register (PWM0LER -
0xE001 4050 and PWM1LER 0xE001 8050) 645
UM10237
© NXP B.V. 2009. All rights reserved.
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