LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 278
![IC ARM7 MCU FLASH 512K 208TFBGA](/photos/12/32/123248/mfg_lpc24xx_sml.jpg)
LPC2468FET208,551
Manufacturer Part Number
LPC2468FET208,551
Description
IC ARM7 MCU FLASH 512K 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2468FET208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2S/ISP/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
6
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
Development Tools By Supplier
OM10100
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4262
935283234551
LPC2468FET208-S
935283234551
LPC2468FET208-S
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
LPC2468FET208,551
Manufacturer:
NXP
Quantity:
6 174
Company:
Part Number:
LPC2468FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
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UM10237_4
User manual
The flexibility of the descriptors used in the Ethernet block allows the possibility of defining
memory buffers in a range of sizes. In order to analyze bus bandwidth requirements,
some assumptions must be made about these buffers. The "worst case" is not addressed
since that would involve all descriptors pointing to single byte buffers, with most of the
memory occupied in holding descriptors and very little data. It can easily be shown that
the AHB cannot handle the huge amount of bus traffic that would be caused by such a
degenerate (and illogical) case.
For this analysis, an Ethernet packet is assumed to consist of a 64 byte frame.
Continuous traffic is assumed on both the transmit and receive channels.
This analysis does not reflect the flow of Ethernet traffic over time, which would include
inter-packet gaps in both the transmit and receive channels that reduce the bandwidth
requirements over a larger time frame.
Types of DMA access and their bandwidth requirements
The interface to an external Ethernet PHY is via either MII or RMII. An MII operates at
25 MHz, transferring a byte in 2 clock cycles. An RMII operates at 50 MHz , transferring a
byte in 4 clock cycles. The data transfer rate is the same in both cases: 12.5 Mbps.
The Ethernet block initiates DMA accesses for the following cases:
•
•
•
•
•
•
Tx descriptor read:
– Transmit descriptors occupy 2 words (8 bytes) of memory and are read once for
– Two word read happens once every 64 bytes (16 words) of transmitted data.
– This gives 1/8th of the data rate, which = 1.5625 Mbps.
Rx descriptor read:
– Receive descriptors occupy 2 words (8 bytes) of memory and are read once for
– Two word read happens once every 64 bytes (16 words) of received data.
– This gives 1/8th of the data rate, which = 1.5625 Mbps.
Tx status write:
– Transmit status occupies 1 word (4 bytes) of memory and is written once for each
– One word write happens once every 64 bytes (16 words) of transmitted data.
– This gives 1/16th of the data rate, which = 0.7813 Mbps.
Rx status write:
– Receive status occupies 2 words (8 bytes) of memory and is written once for each
– Two word write happens once every 64 bytes (16 words) of received data.
– This gives 1/8 of the data rate, which = 1.5625 Mbps.
Tx data read:
– Data transmitted in an Ethernet frame, the size is variable.
– Basic Ethernet rate = 12.5 Mbps.
Rx data write:
each use of a descriptor.
each use of a descriptor.
use of a descriptor.
use of a descriptor.
Rev. 04 — 26 August 2009
Chapter 11: LPC24XX Ethernet
UM10237
© NXP B.V. 2009. All rights reserved.
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