S9S08SG8E2MTJ Freescale Semiconductor, S9S08SG8E2MTJ Datasheet - Page 152

• Manufacturer Part Number: S9S08SG8E2MTJ
• Description: MCU 2K FLASH 20-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08SG8E2MTJ

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-TSSOP
• Processor Series: S08SG
• Core: HCS08
• Data Bus Width: 8 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 10 Internal Clock Source (S08ICSV2)
10.3.3
10.3.4
152
IREFST
CLKST
Field
TRIM
Field
3-2
7:0
7:5
4
Reset:
Reset:
POR:
POR:
W
W
R
R
ICS Trim Register (ICSTRM)
ICS Status and Control (ICSSC)
ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal
reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).
Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period.
An additional fine trim bit is available in ICSSC as the FTRIM bit.
Reserved, should be cleared.
Internal Reference Status — The IREFST bit indicates the current source for the reference clock. The IREFST
bit does not update immediately after a write to the IREFS bit due to internal synchronization between clock
domains.
0 Source of reference clock is external clock.
1 Source of reference clock is internal clock.
Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits don’t update
immediately after a write to the CLKS bits due to internal synchronization between clock domains.
00
01
10
11
Output of FLL is selected.
FLL Bypassed, Internal reference clock is selected.
FLL Bypassed, External reference clock is selected.
Reserved.
U
7
1
7
0
0
0
Table 10-5. ICS Status and Control Register Field Descriptions
Figure 10-6. ICS Status and Control Register (ICSSC)
Table 10-4. ICS Trim Register Field Descriptions
U
0
0
0
0
6
6
Figure 10-5. ICS Trim Register (ICSTRM)
MC9S08SG8 MCU Series Data Sheet, Rev. 6
U
0
0
0
0
5
5
IREFST
U
0
1
1
4
4
Description
Description
TRIM
U
0
0
0
3
3
CLKST
U
0
0
0
2
2
OSCINIT
Freescale Semiconductor
U
0
0
0
1
1
FTRIM
U
U
0
0
0
0