S9S08SG8E2MTJ Freescale Semiconductor, S9S08SG8E2MTJ Datasheet - Page 260

• Manufacturer Part Number: S9S08SG8E2MTJ
• Description: MCU 2K FLASH 20-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08SG8E2MTJ

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-TSSOP
• Processor Series: S08SG
• Core: HCS08
• Data Bus Width: 8 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 16 Timer/PWM Module (S08TPMV3)
260
TPMxCNTH:TPMxCNTL
TPMxMODH:TPMxMODL = 0x0007
TPMxCnVH:TPMxCnVL = 0x0005
EPWM mode
6. Write to TPMxMODH:L registers in BDM mode
7. Update of EPWM signal when CLKSB:CLKSA = 00
(in TPMv2 and TPMv3)
TPMv2 TPMxCHn
CLKSB:CLKSA BITS
TPMv3 TPMxCHn
ELSnB:ELSnA BITS
RESET (active low)
MSnB:MSnA BITS
— TPMxCnVH:L is changed from a non-zero value to 0x0000 [SE110-TPM case 4]
Registers
In the TPM v3 a write to TPMxSC register in BDM mode clears the write coherency mechanism
of TPMxMODH:L registers. Instead, in the TPM v2 this coherency mechanism is not cleared when
there is a write to TPMxSC register.
In the TPM v3 if CLKSB:CLKSA = 00, then the EPWM signal in the channel output is not update
(it is frozen while CLKSB:CLKSA = 00). Instead, in the TPM v2 the EPWM signal is updated at
the next rising edge of bus clock after a write to TPMxCnSC register.
The
after the reset (CLKSB:CLKSA = 00) and if there is a write to TPMxCnSC register.
BUS CLOCK
In this case, the TPM v3 waits for the start of a new PWM period to begin using the new duty
cycle setting. Instead, the TPM v2 changes the channel output at the middle of the current
PWM period (when the count reaches 0x0000).
In this case, the TPM v3 finishes the current PWM period using the old duty cycle setting.
Instead, the TPM v2 finishes the current PWM period using the new duty cycle setting.
Figure 0-1
Figure 0-1. Generation of high-true EPWM signal by TPM v2 and v3 after the reset
CHnF BIT
(TPMxMODH:TPMxMODL))
and
Figure 0-2
00
00
MC9S08SG8 MCU Series Data Sheet, Rev. 6
show when the EPWM signals generated by TPM v2 and TPM v3
00
0
(Section 16.3.3, “TPM Counter Modulo
10
10
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Freescale Semiconductor
01
0 1
2
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