S9S08SG8E2MTJ Freescale Semiconductor, S9S08SG8E2MTJ Datasheet - Page 88

• Manufacturer Part Number: S9S08SG8E2MTJ
• Description: MCU 2K FLASH 20-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08SG8E2MTJ

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-TSSOP
• Processor Series: S08SG
• Core: HCS08
• Data Bus Width: 8 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 6 Parallel Input/Output Control
6.6.3.5
6.6.3.6
87
PTCDS[3:0]
GNGP[7:1]
Reset:
Reset:
GNGEN
Field
Field
3:0
7:1
0
W
W
R
R
GNGPS7
Output Drive Strength Selection for Port C Bits — Each of these control bits selects between low and high
output drive for the associated PTC pin. For port C pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port C bit n.
1 High output drive strength selected for port C bit n.
Ganged Output Pin Select Bits— These write-once control bits selects whether the associated pin (see
Table
be controlled by the data, drive strength and slew rate settings for PTC0.
0 Associated pin is not part of the ganged output drive.
1 Associated pin is part of the ganged output drive. Requires GNGEN = 1.
Ganged Output Drive Enable Bit— This write-once control bit selects whether the ganged output drive feature
is enabled.
0 Ganged output drive disabled.
1 Ganged output drive enabled. PTC0 forced to output regardless of the value of PTCDD0 in PTCDD.
Port C Drive Strength Selection Register (PTCDS)
0
0
Ganged Output Drive Control Register (GNGC)
0
7
7
6-1for pins available) is enabled for ganged output. When GNGEN = 1, all enabled ganged output pins will
Figure 6-23. Drive Strength Selection for Port C Register (PTCDS)
GNGPS6
Figure 6-24. Ganged Output Drive Control Register (GNGC)
0
0
0
6
6
Table 6-22. PTCDS Register Field Descriptions
Table 6-23. GNGC Register Field Descriptions
MC9S08SG8 MCU Series Data Sheet, Rev. 6
GNGPS5
0
0
0
5
5
GNGPS4
0
0
0
4
4
Description
Description
GNGPS3
PTCDS3
3
0
3
0
GNGPS2
PTCDS2
0
0
2
2
GNGPS1
PTCDS1
Freescale Semiconductor
0
0
1
1
PTCDS0
GNGEN
0
0
0
0