MC9S08SH16MTG Freescale Semiconductor, MC9S08SH16MTG Datasheet - Page 107

• Manufacturer Part Number: MC9S08SH16MTG
• Description: MCU 8BIT 16K FLASH 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08SH16MTG

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Core: S08
• Processor Series: MC9S08Sxx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Height: 1.05 mm
• Interface Type: SCI, SPI, I2C
• Length: 5 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 4.4 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
MOV opr8a,opr8a
MOV opr8a,X+
MOV #opr8i,opr8a
MOV ,X+,opr8a
MUL
NEG opr8a
NEGA
NEGX
NEG oprx8,X
NEG ,X
NEG oprx8,SP
NOP
NSA
ORA #opr8i
ORA opr8a
ORA opr16a
ORA oprx16,X
ORA oprx8,X
ORA ,X
ORA oprx16,SP
ORA oprx8,SP
PSHA
PSHH
PSHX
PULA
PULH
PULX
ROL opr8a
ROLA
ROLX
ROL oprx8,X
ROL ,X
ROL oprx8,SP
ROR opr8a
RORA
RORX
ROR oprx8,X
ROR ,X
ROR oprx8,SP
Source
Form
Move
(M)
In IX+/DIR and DIR/IX+ Modes,
H:X ← (H:X) + $0001
Unsigned multiply
X:A ← (X) × (A)
Negate
(Two’s Complement) A ← – (A) = $00 – (A)
No Operation — Uses 1 Bus Cycle
Nibble Swap Accumulator
A ← (A[3:0]:A[7:4])
Inclusive OR Accumulator and Memory
A ← (A) | (M)
Push Accumulator onto Stack
Push (A); SP ← (SP) – $0001
Push H (Index Register High) onto Stack
Push (H); SP ← (SP) – $0001
Push X (Index Register Low) onto Stack
Push (X); SP ← (SP) – $0001
Pull Accumulator from Stack
SP ← (SP + $0001); Pull (A)
Pull H (Index Register High) from Stack
SP ← (SP + $0001); Pull (H)
Pull X (Index Register Low) from Stack
SP ← (SP + $0001); Pull (X)
Rotate Left through Carry
Rotate Right through Carry
destination
C
b7
b7
← (M)
Table 7-2. Instruction Set Summary (Sheet 6 of 9)
Operation
source
b0
M ← – (M) = $00 – (M)
X ← – (X) = $00 – (X)
M ← – (M) = $00 – (M)
M ← – (M) = $00 – (M)
M ← – (M) = $00 – (M)
b0
C
MC9S08SH32 Series Data Sheet, Rev. 2
PRELIMINARY
DIR/DIR
DIR/IX+
IMM/DIR
IX+/DIR
INH
DIR
INH
INH
IX1
IX
SP1
INH
INH
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
INH
INH
INH
INH
INH
INH
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
Object Code
9E 60
9E DA
9E EA
9E 69
9E 66
4E
5E
6E
7E
42
30
40
50
60
70
9D
62
AA
BA
CA
DA
EA
FA
87
8B
89
86
8A
88
39
49
59
69
79
36
46
56
66
76
dd dd
dd
ii dd
dd
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ee ff
ff
dd
ff
ff
dd
ff
ff
Chapter 7 Central Processor Unit (S08CPUV3)
5
5
4
5
5
5
1
1
5
4
6
1
1
2
3
4
4
3
3
5
4
2
2
2
3
3
3
5
1
1
5
4
6
5
1
1
5
4
6
rpwpp
rfwpp
pwpp
rfwpp
ffffp
rfwpp
p
p
rfwpp
rfwp
prfwpp
p
p
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
sp
sp
sp
ufp
ufp
ufp
rfwpp
p
p
rfwpp
rfwp
prfwpp
rfwpp
p
p
rfwpp
rfwp
prfwpp
Cyc-by-Cyc
Details
V 1 1 H I N Z C
↕ 1 1 – – ↕ ↕ ↕
↕ 1 1 – – ↕ ↕ ↕
0 1 1 – – ↕ ↕ –
– 1 1 0 – – – 0
– 1 1 – – – – –
– 1 1 – – – – –
0 1 1 – – ↕ ↕ –
– 1 1 – – – – –
– 1 1 – – – – –
– 1 1 – – – – –
– 1 1 – – – – –
– 1 1 – – – – –
– 1 1 – – – – –
↕ 1 1 – – ↕ ↕ ↕
on CCR
Affect
107