MC9S08SH16MTG Freescale Semiconductor, MC9S08SH16MTG Datasheet - Page 230

• Manufacturer Part Number: MC9S08SH16MTG
• Description: MCU 8BIT 16K FLASH 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08SH16MTG

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Core: S08
• Processor Series: MC9S08Sxx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Height: 1.05 mm
• Interface Type: SCI, SPI, I2C
• Length: 5 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 4.4 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 15 Serial Peripheral Interface (S08SPIV3)
Ensure that the SPI should not be disabled (SPE=0) at the same time as a bit change to the CPHA bit. These
changes should be performed as separate operations or unexpected behavior may occur.
15.4.2
This read/write register is used to control optional features of the SPI system. Bits 7, 6, 5, and 2 are not
implemented and always read 0.
230
Reset
LSBFE
MSTR
CPHA
SSOE
CPOL
Field
4
3
2
1
0
W
R
SPI Control Register 2 (SPIxC2)
Master/Slave Mode Select
0 SPI module configured as a slave SPI device
1 SPI module configured as a master SPI device
Clock Polarity — This bit effectively places an inverter in series with the clock signal from a master SPI or to a
slave SPI device. Refer to
0 Active-high SPI clock (idles low)
1 Active-low SPI clock (idles high)
Clock Phase — This bit selects one of two clock formats for different kinds of synchronous serial peripheral
devices. Refer to
0 First edge on SPSCK occurs at the middle of the first cycle of an 8-cycle data transfer
1 First edge on SPSCK occurs at the start of the first cycle of an 8-cycle data transfer
Slave Select Output Enable — This bit is used in combination with the mode fault enable (MODFEN) bit in
SPCR2 and the master/slave (MSTR) control bit to determine the function of the SS pin as shown in
LSB First (Shifter Direction)
0 SPI serial data transfers start with most significant bit
1 SPI serial data transfers start with least significant bit
MODFEN
0
0
7
0
0
1
1
= Unimplemented or Reserved
0
0
6
Section 15.5.1, “SPI Clock
SSOE
Table 15-1. SPIxC1 Field Descriptions (continued)
0
1
0
1
Figure 15-6. SPI Control Register 2 (SPIxC2)
Section 15.5.1, “SPI Clock
MC9S08SH32 Series Data Sheet, Rev. 2
General-purpose I/O (not SPI)
General-purpose I/O (not SPI)
SS input for mode fault
Automatic SS output
0
0
5
Table 15-2. SS Pin Function
PRELIMINARY
MODFEN
Master Mode
NOTE
Formats”
0
4
Description
Formats”
for more details.
BIDIROE
3
0
for more details.
Slave select input
Slave select input
Slave select input
Slave select input
0
0
2
Slave Mode
SPISWAI
Freescale Semiconductor
0
1
Table
SPC0
0
0
15-2.