MC9S08SH16MTG Freescale Semiconductor, MC9S08SH16MTG Datasheet - Page 179

• Manufacturer Part Number: MC9S08SH16MTG
• Description: MCU 8BIT 16K FLASH 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08SH16MTG

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Core: S08
• Processor Series: MC9S08Sxx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Height: 1.05 mm
• Interface Type: SCI, SPI, I2C
• Length: 5 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 4.4 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

11.4.1.5
The FLL bypassed external (FBE) mode is entered when all the following conditions occur:
In FLL bypassed external mode, the ICSOUT clock is derived from the external reference clock. The FLL
clock is controlled by the external reference clock, and the FLL loop will lock the FLL frequency to 1024
times the reference frequency, as selected by the RDIV bits, so that the ICSLCLK will be available for
BDC communications, and the external reference clock is enabled.
11.4.1.6
The FLL bypassed external low power (FBELP) mode is entered when all the following conditions occur:
In FLL bypassed external low power mode, the ICSOUT clock is derived from the external reference clock
and the FLL is disabled. The ICSLCLK will be not be available for BDC communications. The external
reference clock is enabled.
11.4.1.7
Stop mode is entered whenever the MCU enters a STOP state. In this mode, all ICS clock signals are static
except in the following cases:
ICSIRCLK will be active in stop mode when all the following conditions occur:
ICSERCLK will be active in stop mode when all the following conditions occur:
11.4.2
When switching between FLL engaged internal (FEI) and FLL engaged external (FEE) modes the IREFS
bit can be changed at anytime, but the RDIV bits must be changed simultaneously so that the resulting
frequency stays in the range of 31.25 kHz to 39.0625 kHz. After a change in the IREFS value the FLL will
begin locking again after a few full cycles of the resulting divided reference frequency. The completion of
the switch is shown by the IREFST bit.
Freescale Semiconductor
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CLKS bits are written to 10.
IREFS bit is written to 0.
BDM mode is active or LP bit is written to 0.
CLKS bits are written to 10.
IREFS bit is written to 0.
BDM mode is not active and LP bit is written to 1.
IRCLKEN bit is written to 1
IREFSTEN bit is written to 1
ERCLKEN bit is written to 1
EREFSTEN bit is written to 1
Mode Switching
FLL Bypassed External (FBE)
FLL Bypassed External Low Power (FBELP)
Stop
MC9S08SH32 Series Data Sheet, Rev. 2
PRELIMINARY
Chapter 11 Internal Clock Source (S08ICSV2)
179