MC9S08SH16MTG Freescale Semiconductor, MC9S08SH16MTG Datasheet - Page 3

• Manufacturer Part Number: MC9S08SH16MTG
• Description: MCU 8BIT 16K FLASH 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08SH16MTG

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Core: S08
• Processor Series: MC9S08Sxx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Height: 1.05 mm
• Interface Type: SCI, SPI, I2C
• Length: 5 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 4.4 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

MC9S08SH32 Series Features
8-Bit HCS08 Central Processor Unit (CPU)
On-Chip Memory
Power-Saving Modes
Clock Source Options
System Protection
Development Support
• 40-MHz HCS08 CPU (central processor unit)
• HC08 instruction set with added BGND instruction
• Support for up to 32 interrupt/reset sources
• FLASH read/program/erase over full operating
• Random-access memory (RAM)
• Security circuitry to prevent unauthorized access
• Two very low power stop modes
• Reduced power wait mode
• Very low power real time counter for use in run,
• Oscillator (XOSC) — Loop-control Pierce
• Internal Clock Source (ICS) — Internal clock
• ICS supports bus frequencies from 2 MHz to
• Watchdog computer operating properly (COP)
• Low-voltage detection with reset or interrupt;
• Illegal opcode detection with reset
• Illegal address detection with reset
• FLASH block protect
• Single-wire background debug interface
• Breakpoint capability to allow single breakpoint
• On-chip, in-circuit emulation (ICE) debug module
voltage and temperature
to RAM and FLASH contents
wait, and stop
oscillator; Crystal or ceramic resonator range of
31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz
source module containing a frequency-locked
loop (FLL) controlled by internal or external
reference; precision trimming of internal reference
allows 0.2% resolution and 2% deviation over
temperature and voltage; 1.5% deviation using
internal temperature compensation.
20 MHz.
reset with option to run from dedicated 1-kHz
internal clock source or bus clock
selectable trip points
setting during in-circuit debugging (plus two more
breakpoints in on-chip debug module)
containing two comparators and nine trigger
modes. Eight deep FIFO for storing
change-of-flow address and event-only data.
Debug module supports both tag and force
breakpoints.
PRELIMINARY
Peripherals
Input/Output
Package Options
• ADC — 16-channel, 10-bit resolution, 2.5 μs
• ACMP — Analog comparators with selectable
• SCI — Full duplex non-return to zero (NRZ); LIN
• SPI — Full-duplex or single-wire bidirectional;
• IIC — Up to 100 kbps with maximum bus loading;
• MTIM — 8-bit modulo counter with 8-bit prescaler
• TPMx — Two 2-channel timer pwm modules
• RTC — (Real-time counter) 8-bit modulus counter
• 23 general purpose I/O pins (GPIOs) and 1
• 8 interrupt pins with selectable polarity
• Ganged output option for PTB[5:2] and PTC[3:0];
• Hysteresis and configurable pull up device on all
• 28-TSSOP, 28-SOIC, 20-TSSOP, 16-TSSOP
conversion time, automatic compare function,
temperature sensor, internal bandgap reference
channel; runs in stop3
interrupt on rising, falling, or either edge of
comparator output; compare option to fixed
internal bandgap reference voltage; output can be
optionally routed to TPM module; runs in stop3
master extended break generation; LIN slave
extended break detection; wake up on active edge
Double-buffered transmit and receive; Master or
Slave mode; MSB-first or LSB-first shifting
Multi-master operation; Programmable slave
address; Interrupt driven byte-by-byte data
transfer; supports broadcast mode and 10-bit
addressing
and overflow interrupt
(TPM1, TPM2); Selectable input capture, output
compare, or buffered edge- or center-aligned
PWM on each channel
with binary or decimal based prescaler; External
clock source for precise time base, time-of-day,
calendar or task scheduling functions; Free
running on-chip low power oscillator (1 kHz) for
cyclic wake-up without external components, runs
in all MCU modes
output-only pin
allows single write to change state of multiple pins
input pins; Configurable slew rate and drive
strength on all output pins.