MC9S08SH16MTG Freescale Semiconductor, MC9S08SH16MTG Datasheet - Page 175

• Manufacturer Part Number: MC9S08SH16MTG
• Description: MCU 8BIT 16K FLASH 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08SH16MTG

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Core: S08
• Processor Series: MC9S08Sxx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Height: 1.05 mm
• Interface Type: SCI, SPI, I2C
• Length: 5 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 4.4 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

11.3.2
Freescale Semiconductor
EREFSTEN
ERCLKEN
RANGE
EREFS
Field
BDIV
HGO
7:6
LP
5
4
3
2
1
0
Reset:
W
R
ICS Control Register 2 (ICSC2)
Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bits. This
controls the bus frequency.
00
01
10
11
Frequency Range Select — Selects the frequency range for the external oscillator.
1 High frequency range selected for the external oscillator
0 Low frequency range selected for the external oscillator
High Gain Oscillator Select — The HGO bit controls the external oscillator mode of operation.
1 Configure external oscillator for high gain operation
0 Configure external oscillator for low power operation
Low Power Select — The LP bit controls whether the FLL is disabled in FLL bypassed modes.
1 FLL is disabled in bypass modes unless BDM is active
0 FLL is not disabled in bypass mode
External Reference Select — The EREFS bit selects the source for the external reference clock.
1 Oscillator requested
0 External Clock Source requested
External Reference Enable — The ERCLKEN bit enables the external reference clock for use as ICSERCLK.
1 ICSERCLK active
0 ICSERCLK inactive
External Reference Stop Enable — The EREFSTEN bit controls whether or not the external reference clock
remains enabled when the ICS enters stop mode.
1 External reference clock stays enabled in stop if ERCLKEN is set or if ICS is in FEE, FBE, or FBELP mode
0 External reference clock is disabled in stop
before entering stop
Encoding 0 — Divides selected clock by 1
Encoding 1 — Divides selected clock by 2 (reset default)
Encoding 2 — Divides selected clock by 4
Encoding 3 — Divides selected clock by 8
0
7
BDIV
Table 11-3. ICS Control Register 2 Field Descriptions
1
6
Figure 11-4. ICS Control Register 2 (ICSC2)
MC9S08SH32 Series Data Sheet, Rev. 2
RANGE
5
0
PRELIMINARY
HGO
0
4
Description
LP
0
3
Chapter 11 Internal Clock Source (S08ICSV2)
EREFS
0
2
ERCLKEN EREFSTEN
0
1
0
0
175