MC9S08AC60CFDE Freescale Semiconductor, MC9S08AC60CFDE Datasheet - Page 118

• Manufacturer Part Number: MC9S08AC60CFDE
• Description: IC MCU 8BIT 60K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08AC60CFDE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Processor Series: S08AC
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08AC60E, DEMOACEX, DEMOACKIT, DCF51AC256, DC9S08AC128, DC9S08AC16, DC9S08AC60, DEMO51AC256KIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Controller Family/series: HCS08
• No. Of I/o's: 38
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Height: 1 mm
• Length: 7 mm
• Supply Voltage (max): 5.5 V, 5.5 V
• Supply Voltage (min): 2.7 V, 2.7 V
• Width: 7 mm
• For Use With: DEMO9S08AC60E - BOARD DEMO FOR MC9S08A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 7 Central Processor Unit (S08CPUV2)
118
BPL rel
BRA rel
BRCLR n,opr8a,rel
BRN rel
BRSET n,opr8a,rel
BSET n,opr8a
BSR rel
CBEQ opr8a,rel
CBEQA #opr8i,rel
CBEQX #opr8i,rel
CBEQ oprx8,X+,rel
CBEQ ,X+,rel
CBEQ oprx8,SP,rel
CLC
CLI
CLR opr8a
CLRA
CLRX
CLRH
CLR oprx8,X
CLR ,X
CLR oprx8,SP
Source
Form
Branch if Plus (if N = 0)
Branch Always (if I = 1)
Branch if Bit n in Memory Clear (if (Mn) = 0)
Branch Never (if I = 0)
Branch if Bit n in Memory Set (if (Mn) = 1)
Set Bit n in Memory (Mn ← 1)
Branch to Subroutine
Compare and...
Clear Carry Bit (C ← 0)
Clear Interrupt Mask Bit (I ← 0)
Clear
push (PCH); SP ← (SP) – $0001
push (PCL); SP ← (SP) – $0001
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
PC ← (PC) + $0002
PC ← (PC) + rel
Table 7-2. Instruction Set Summary (Sheet 3 of 9)
Operation
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (X) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
MC9S08AC60 Series Data Sheet, Rev. 2
REL
REL
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
DIR
IMM
IMM
IX1+
IX+
SP1
INH
INH
DIR
INH
INH
INH
IX1
IX
SP1
Object Code
9E 61
9E 6F
2A rr
20 rr
01
03
05
07
09
0B
0D
0F
21 rr
00
02
04
06
08
0A
0C
0E
10
12
14
16
18
1A
1C
1E
AD rr
31
41
51
61
71
98
9A
3F
4F
5F
8C
6F
7F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd
dd
dd
dd
dd
dd
dd
dd
dd rr
ii rr
ii rr
ff rr
rr
ff rr
dd
ff
ff
3
3
5
5
5
5
5
5
5
5
3
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
5
5
6
1
1
5
1
1
1
5
4
6
ppp
ppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
ppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
ssppp
rpppp
pppp
pppp
rpppp
rfppp
prpppp
p
p
rfwpp
p
p
p
rfwpp
rfwp
prfwpp
Cyc-by-Cyc
Details
Freescale Semiconductor
V 1 1 H I N Z C
– 1 1 – – – – –
– 1 1 – – – – –
– 1 1 – – – – ↕
– 1 1 – – – – –
– 1 1 – – – – ↕
– 1 1 – – – – –
– 1 1 – – – – –
– 1 1 – – – – –
– 1 1 – – – – 0
– 1 1 – 0 – – –
0 1 1 – – 0 1 –
on CCR
Affect