MC9S08AC60CFDE Freescale Semiconductor, MC9S08AC60CFDE Datasheet - Page 278
![IC MCU 8BIT 60K FLASH 48-QFN](/photos/12/34/123442/mc9s08ac60cfde_sml.jpg)
MC9S08AC60CFDE
Manufacturer Part Number
MC9S08AC60CFDE
Description
IC MCU 8BIT 60K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08AC60CFJE.pdf
(348 pages)
Specifications of MC9S08AC60CFDE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Processor Series
S08AC
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08AC60E, DEMOACEX, DEMOACKIT, DCF51AC256, DC9S08AC128, DC9S08AC16, DC9S08AC60, DEMO51AC256KIT
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Controller Family/series
HCS08
No. Of I/o's
38
Ram Memory Size
2KB
Cpu Speed
40MHz
No. Of Timers
3
Rohs Compliant
Yes
Height
1 mm
Length
7 mm
Supply Voltage (max)
5.5 V, 5.5 V
Supply Voltage (min)
2.7 V, 2.7 V
Width
7 mm
For Use With
DEMO9S08AC60E - BOARD DEMO FOR MC9S08A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- Current page: 278 of 348
- Download datasheet (4Mb)
Chapter 15 Timer/PWM Module (S08TPMV3)
278
3. Read of TPMxCnVH:L registers
4. Write to TPMxCnVH:L registers
5. Center-Aligned PWM
— This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to
(TPMxCnVH:TPMxCnVL))
— In TPM v3, any read of TPMxCnVH:L registers during BDM mode returns the value of the
— This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to
— Input Capture Mode
— Output Compare Mode
— Edge-Aligned PWM
— Center-Aligned PWM
— TPMxCnVH:L = TPMxMODH:L [SE110-TPM case 1]
BDM mode returns the latched value of TPMxCNTH:L from the read buffer instead of the
frozen TPM counter value.
TPMxSC, TPMxCNTH or TPMxCNTL. Instead, in these conditions the TPM v2 does not clear
this read coherency mechanism.
TPMxCnVH:L register. In TPM v2, if only one byte of the TPMxCnVH:L registers was read
before the BDM mode became active, then any read of TPMxCnVH:L registers during BDM
mode returns the latched value of TPMxCNTH:L from the read buffer instead of the value in
the TPMxCnVH:L registers.
TPMxCnSC. Instead, in this condition the TPM v2 does not clear this read coherency
mechanism.
In this mode the TPM v3 does not allow the writes to TPMxCnVH:L registers. Instead, the
TPM v2 allows these writes.
In this mode and if (CLKSB:CLKSA not = 0:0), the TPM v3 updates the TPMxCnVH:L
registers with the value of their write buffer at the next change of the TPM counter (end of the
prescaler counting) after the second byte is written. Instead, the TPM v2 always updates these
registers when their second byte is written.
In this mode and if (CLKSB:CLKSA not = 00), the TPM v3 updates the TPMxCnVH:L
registers with the value of their write buffer after that the both bytes were written and when the
TPM counter changes from (TPMxMODH:L - 1) to (TPMxMODH:L). If the TPM counter is
a free-running counter, then this update is made when the TPM counter changes from $FFFE
to $FFFF. Instead, the TPM v2 makes this update after that the both bytes were written and
when the TPM counter changes from TPMxMODH:L to $0000.
In this mode and if (CLKSB:CLKSA not = 00), the TPM v3 updates the TPMxCnVH:L
registers with the value of their write buffer after that the both bytes were written and when the
TPM counter changes from (TPMxMODH:L - 1) to (TPMxMODH:L). If the TPM counter is
a free-running counter, then this update is made when the TPM counter changes from $FFFE
to $FFFF. Instead, the TPM v2 makes this update after that the both bytes were written and
when the TPM counter changes from TPMxMODH:L to (TPMxMODH:L - 1).
In this case, the TPM v3 produces 100% duty cycle. Instead, the TPM v2 produces 0% duty
cycle.
(Section 15.6.2.4, “Center-Aligned PWM
(Section 15.6.2.1, “Input Capture
(Section 15.6.2.3, “Edge-Aligned PWM
(Section 15.6.2.4, “Center-Aligned PWM
(Section 15.6.2.2, “Output Compare
MC9S08AC60 Series Data Sheet, Rev. 2
(Section 15.5.5, “TPM Channel Value Registers
Mode)
Mode)
Mode)
Mode)
Mode)
Freescale Semiconductor
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