MC9S08AC60CFDE Freescale Semiconductor, MC9S08AC60CFDE Datasheet - Page 193

IC MCU 8BIT 60K FLASH 48-QFN

MC9S08AC60CFDE

Manufacturer Part Number
MC9S08AC60CFDE
Description
IC MCU 8BIT 60K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08AC60CFDE

Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Processor Series
S08AC
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08AC60E, DEMOACEX, DEMOACKIT, DCF51AC256, DC9S08AC128, DC9S08AC16, DC9S08AC60, DEMO51AC256KIT
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Controller Family/series
HCS08
No. Of I/o's
38
Ram Memory Size
2KB
Cpu Speed
40MHz
No. Of Timers
3
Rohs Compliant
Yes
Height
1 mm
Length
7 mm
Supply Voltage (max)
5.5 V, 5.5 V
Supply Voltage (min)
2.7 V, 2.7 V
Width
7 mm
For Use With
DEMO9S08AC60E - BOARD DEMO FOR MC9S08A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Refer to the direct-page register summary in the
assignments for all IIC registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
11.3.1
11.3.2
Freescale Semiconductor
Reset
Reset
AD[7:1]
Field
7–1
W
W
R
R
IIC Address Register (IICA)
IIC Frequency Divider Register (IICF)
AD7
Slave Address. The AD[7:1] field contains the slave address to be used by the IIC module. This field is used on
the 7-bit address scheme and the lower seven bits of the 10-bit address scheme.
0
0
7
7
MULT
= Unimplemented or Reserved
AD6
0
0
6
6
Figure 11-4. IIC Frequency Divider Register (IICF)
Figure 11-3. IIC Address Register (IICA)
MC9S08AC60 Series Data Sheet, Rev. 2
Table 11-1. IICA Field Descriptions
AD5
0
0
5
5
memory
AD4
0
0
4
4
Description
chapter of this document for the absolute address
AD3
3
0
3
0
ICR
Chapter 11 Inter-Integrated Circuit (S08IICV2)
AD2
0
0
2
2
AD1
0
0
1
1
0
0
0
0
0
193

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