MC908GR4CDWE Freescale Semiconductor, MC908GR4CDWE Datasheet - Page 128

• Manufacturer Part Number: MC908GR4CDWE
• Description: IC MCU 4K FLASH 8MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR4CDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Low-Voltage Inhibit (LVI)
LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register (CONFIG). See
8 Configuration Register (CONFIG)
the MCU remains in reset until V
See
The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
14.3.1 Polled LVI Operation
In applications that can operate at V
the LVIOUT bit. In the configuration register, the LVIPWRD bit must be 0 to enable the LVI module, and
the LVIRSTD bit must be 1 to disable LVI resets.
14.3.2 Forced Reset Operation
In applications that require V
module to reset the MCU when V
LVIPWRD and LVIRSTD bits must be cleared to enable the LVI module and to enable LVI resets.
14.3.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having V
V
continually entering and exiting reset if V
V
128
Addr.
$FE0C
DD
TRIPF
19.3.2.5 Low-Voltage Inhibit (LVI) Reset
rises above the rising trip point voltage, V
by the hysteresis voltage, V
Register Name
LVI Status Register
FROM CONFIG
DETECTOR
LVI5OR3
LOW V
(LVISR)
V
DD
DD
Reset:
Read:
Write:
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
DD
Figure 14-1. LVI Module Block Diagram
Figure 14-2. LVI I/O Register Summary
V
V
to remain above the V
DD
DD
DD
DD
FROM CONFIG
LVIOUT
> LVI
≤ LVI
HYS
Bit 7
DD
rises above a voltage, V
for details of the LVI’s configuration bits. Once an LVI reset occurs,
LVIPWRD
falls below the V
0
Trip
Trip
levels below the V
.
DD
= 0
= 1
DD
= Unimplemented
fall below V
is approximately equal to V
for details of the interaction between the SIM and the LVI.
6
0
0
TRIPR
LVIOUT
. This prevents a condition in which the MCU is
TRIPF
TRIPF
5
TRIPF
STOP INSTRUCTION
0
0
FROM CONFIG
TRIPF
LVIRSTD
level. In the configuration register, the
), the LVI will maintain a reset condition until
level, enabling LVI resets allows the LVI
TRIPR
level, software can monitor V
4
0
0
, which causes the MCU to exit reset.
TRIPF
3
0
0
FROM CONFIG
. V
LVISTOP
LVI RESET
TRIPR
2
0
0
Freescale Semiconductor
is greater than
1
0
0
DD
by polling
Chapter
Bit 0
0
0