MC908GR4CDWE Freescale Semiconductor, MC908GR4CDWE Datasheet - Page 44

• Manufacturer Part Number: MC908GR4CDWE
• Description: IC MCU 4K FLASH 8MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR4CDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Resets and Interrupts
4.2.3.1 Power-On Reset
A power-on reset is an internal reset caused by a positive transition on the V
go completely to 0 V to reset the MCU. This distinguishes between a reset and a POR. The POR is not a
brown-out detector, low-voltage detector, or glitch detector.
A power-on reset:
4.2.3.2 COP Reset
A COP reset is an internal reset caused by an overflow of the COP counter. A COP reset sets the COP
bit in the system integration module (SIM) reset status register.
To clear the COP counter and prevent a COP reset, write any value to the COP control register at location
$FFFF.
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Holds the clocks to the CPU and modules inactive for an oscillator stabilization delay of 4096
CGMXCLK cycles
Drives the RST pin low during the oscillator stabilization delay
Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization delay
Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator
stabilization delay
Sets the POR bit in the SIM reset status register and clears all other bits in the register
PORRST
1. PORRST is an internally generated power-on reset pulse.
CGMXCLK
INTERNAL
CGMOUT
RST PIN
RESET
OSC1
(1)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
Figure 4-1. Power-On Reset Recovery
CYCLES
4096
CYCLES
32
CYCLES
32
DD
pin. V
Freescale Semiconductor
DD
at the POR must