D12312SVTEBL25 Renesas Electronics America, D12312SVTEBL25 Datasheet - Page 214

• Manufacturer Part Number: D12312SVTEBL25
• Description: IC H8S MCU ROMLESS 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12312SVTEBL25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412312SVTEBL25; HD6412312SVTEBL25

Section 2 Instruction Descriptions
2.2.57 (1)
SHAL (SHift Arithmetic Left)
Operation
Rd (left arithmetic shift)
Assembly-Language Format
SHAL.B Rd
Operand Size
Byte
Description
This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit to the left. The
most significant bit (bit 7) shifts into the carry flag. The least significant bit (bit 0) is cleared to 0.
Available Registers
Rd: R0L to R7L, R0H to R7H
Operand Format and Number of States Required for Execution
Notes
The SHAL instruction differs from the SHLL instruction in its effect on the overflow flag.
Rev. 4.00 Feb 24, 2006 page 198 of 322
REJ09B0139-0400
Register direct
Addressing
Mode
SHAL (B)
Mnemonic
SHAL.B
C
Rd
MSB
Operands
b7
Rd
. . . . . .
1st byte
1
0
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Set to 1 if an overflow occurs; otherwise
C: Receives the previous value in bit 7.
2nd byte
8
Instruction Format
cleared to 0.
cleared to 0.
cleared to 0.
—
I
rd
UI H
—
—
3rd byte
LSB
b0
—
U
N
0
4th byte
Shift Arithmetic
Z
V
States
No. of
C
1