D12312SVTEBL25 Renesas Electronics America, D12312SVTEBL25 Datasheet - Page 236

• Manufacturer Part Number: D12312SVTEBL25
• Description: IC H8S MCU ROMLESS 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12312SVTEBL25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412312SVTEBL25; HD6412312SVTEBL25

Section 2 Instruction Descriptions
2.2.60 (5)
SHLR (SHift Logical Right)
Operation
ERd (right logical shift)
Assembly-Language Format
SHLR.L ERd
Operand Size
Longword
Description
This instruction shifts the bits in a 32-bit register ERd (destination operand) one bit to the right.
The least significant bit (bit 0) shifts into the carry flag. The most significant bit (bit 31) is cleared
to 0.
Available Registers
ERd: ER0 to ER7
Operand Format and Number of States Required for Execution
Notes
Rev. 4.00 Feb 24, 2006 page 220 of 322
REJ09B0139-0400
Register direct
Addressing
Mode
SHLR (L)
Mnemonic
0
SHLR.L
MSB
b31
ERd
Operands
ERd
.
. . . . . .
.
1st byte
1
.
.
1
Condition Code
H: Previous value remains unchanged.
N: Always cleared to 0.
Z: Set to 1 if the result is zero; otherwise
V: Always cleared to 0.
C: Receives the previous value in bit 0.
.
2nd byte
3
.
Instruction Format
cleared to 0.
—
I
0 erd
UI H
—
LSB
b0
—
3rd byte
—
U
C
N
0
4th byte
Z
Shift Logical
V
0
States
No. of
C
1