D12312SVTEBL25 Renesas Electronics America, D12312SVTEBL25 Datasheet - Page 98

IC H8S MCU ROMLESS 100-QFP

D12312SVTEBL25

Manufacturer Part Number
D12312SVTEBL25
Description
IC H8S MCU ROMLESS 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of D12312SVTEBL25

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412312SVTEBL25
HD6412312SVTEBL25
Section 2 Instruction Descriptions
2.2.18
BSR (Branch to SubRoutine)
Operation
PC
PC + disp
Assembly-Language Format
BSR disp
Operand Size
Description
This instruction branches to a subroutine at a specified address. It pushes the program counter
(PC) value onto the stack as a restart address, then adds a specified displacement to the PC value
and branches to the resulting address. The PC value pushed onto the stack is the address of the
instruction following the BSR instruction. The displacement is a signed 8-bit or 16-bit value, so
the possible branching range is –126 to +128 bytes or –32766 to +32768 bytes from the address of
the BSR instruction.
Operand Format and Number of States Required for Execution
Rev. 4.00 Feb 24, 2006 page 82 of 322
REJ09B0139-0400
Program-counter
relative
Addressing
Mode
@–SP
BSR
PC
Mnemonic
BSR
Operands
d:16
d:8
1st byte 2nd byte 3rd byte 4th byte
5
5
C
5
Instruction Format
Condition Code
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
0
disp
0
I
UI H
disp
U
Branch to Subroutine
N
Normal Advanced
Z
No. of States
3
4
— —
V
C
4
5

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