M30800SAGP#U5 Renesas Electronics America, M30800SAGP#U5 Datasheet - Page 115

• Manufacturer Part Number: M30800SAGP#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

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3
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2
Figure 10.6 Interrupt Response Time
0
C
10.6.4 Interrupt Response Time
1
9
0 .
8 /
B
Figure 10.6 shows an interrupt response time. Interrupt response time is the period between an interrupt
generation and the execution of the first instruction in an interrupt routine. Interrupt response time in-
cludes the period between an interrupt request generation and the completed execution of an instruction
((a) on Figure 10.6) and the period required to perform an interrupt sequence ((b) on Figure 10.6).
Time (a) varies depending on an instruction being executed. The DIV, DIVX and DIVU instructions
require the longest time (a); 42 cycles when an immediate value or register is set as the divisor.
When the divisor is a value in the memory, the following value is added.
X is the number of wait states for a divisor space. Y is the number of wait states for the space that stores
indirect addresses. If X and Y are in an odd address or in 8-bit bus space, the X and Y value must be
doubled.
Table 10.4 lists time (b), shown Figure 10.6.
0
0
0
Interrupt request is generated
2
7
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N
1
o
o r
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(a) Period between an interrupt request generation and the completed execution of an instruction.
(b) Period required to perform an interrupt sequence.
u
1
0
0
p
, 1
0
2
0
• Normal addressing
• Index addressing
• Indirect addressing
• Indirect index addressing
0
5
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Instruction
f o
3
Interrupt response time
3
0
(a)
Interrupt request is acknowledged
Interrupt sequence
: 2 + X
: 3 + X
: 5 + X + 2Y
: 6 + X + 2Y
(b)
Instruction in
interrupt routine
Time
10. Interrupts