M30800SAGP#U5 Renesas Electronics America, M30800SAGP#U5 Datasheet - Page 211

• Manufacturer Part Number: M30800SAGP#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

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R
R
e
E
16.3 Special Mode 1 (I
3
. v
J
2
Table 16.12 I
0
C
I
tions of I
a block diagram of I
interrupts. Tables 16.15 to 16.17 list pin settings.
As shown in Table 16.12, I
"010
the SCLi pin level becomes low ("L") and stabilizes due to a SDAi transmit output via the delay circuit.
Interrupt
1
9
Selectable Function
2
8 /
0 .
B
C mode is a mode to communicate with external devices with a simplified I
0
0
0
2
2
G
7
N
" and the IICM bit in the UiSMR register is set to "1". Output signal from the SDAi pin changes after
1
o
o r
0 -
Item
. v
2
u
1
C mode. Table 16.13 lists register settings, Table 16.14 lists each function. Figure 16.19 shows
0
p
0
, 1
0
2
2
C Mode Specifications
0
0
5
Page 190
2
C mode. Figure 16.20 shows timings for transfer to the UiRB register (i=0 to 4) and
Start condition detect, stop condition detect, no acknowledgment detect, acknowledgment
detect
• Arbitration lost
• SDAi digital delay
• Clock phase setting
2
Selectable from update timing of the ABT bit in the UiRB register.
Refer to 16.3.3 Arbitration
Selectable from no digital delay or 2 to 8 cycle delay of the count source of of the
UiBRG register. Refer to 16.3.5 SDA Output
Selectable from clock delay or no clock delay. Refer to 16.3.4 Transfer Clock
C Mode)
2
C mode is entered when the SMD2 to SMD0 bits in the UiMR register is set to
f o
3
3
0
Specifications
2
16. Serial I/O (Special Function)
C. Table 16.12 lists specifica-