M30800SAGP#U5 Renesas Electronics America, M30800SAGP#U5 Datasheet - Page 192

• Manufacturer Part Number: M30800SAGP#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
3
. v
J
2
Figure 16.4 U0C0 to U4C0 Registers
0
C
1
9
0 .
8 /
B
0
0
0
2
7
G
N
1
o
o r
0 -
. v
UARTi Transmit/Receive Control Register 0
u
1
b7
NOTES:
0
p
0
, 1
0
b6
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
3. The UFORM bit setting is enabled when the SMD2 to SMD0 bits in the UiMR register are set to
4. Set the UiBRG register after the CLK1 and CLK0 bit settings are changed.
1. P7
2
Set the UFORM bit to "1" when setting the SMD2 to SMD0 bits to"010
0
setting them to "100
b5
"001
0
5
0
b4
/TxD2 and P7
2
" (clock syncronous serial I/O mode) or "101
Page 171
b3
b2
b1
1
b0
f o
/SCL2 are ports for the N-channel open drain output, but not for the CMOS output.
2
" (UART mode, 7-bit transfer data) or "110
3
UFORM
TXEPT
3
Symbol
CKPOL
CLK0
CLK1
CRS
CRD
NCH
0
Bit
Symbol
U0C0 to U4C0
Data Output Select
Bit
UiBRG Count
Source Select Bit
CST/RTS Function
Select Bit
Transmit Register
Empty Flag
CTS/RTS Disable
Bit
CLK Polarity
Select Bit
Transfer Format
Select Bit
(1)
Bit Name
(3)
Address
036C
16,
(4)
2
" (UART mode, 8-bit transfer data).
02EC
b1
0 0: Selects f
0 1: Selects f
1 0: Selects f
1 1: Do not set to this value
Enabled when CRD=0
0: Selects CTS function
1: Selects RTS function
0: Data in the transmit register
1: No data in the transmit register
0: Enables CTS/RTS function
1: Disables CTS/RTS function
0: TxDi/SDAi and SCLi are ports for the
1: TxDi/SDAi and SCLi are ports for the
0: Data is transmitted on the falling edge of
1: Data is transmitted on the rising edge of
0: LSB first
1: MSB first
b0
CMOS output
N-channel open drain output
(during transmission)
(transmission is completed)
the transfer clock and data is received
on the rising edge
the transfer clock and data is received
on the falling edge
16,
033C
(i=0 to 4)
2
16,
" (UART mode, 9-bit transfer data).
1
8
2n (2)
032C
2
" (I
Function
16,
2
02FC
C mode), or to "0" when
16
After Reset
0000 1000
2
RW
RW
RW
RW
RW
RW
RW
RW
RO
16. Serial I/O